diff mbox series

[kvm-unit-tests,v2,08/10] x86: Move 32-bit bringup routines to start32.S

Message ID 20220412173407.13637-9-varad.gautam@suse.com (mailing list archive)
State New, archived
Headers show
Series SMP Support for x86 UEFI Tests | expand

Commit Message

Varad Gautam April 12, 2022, 5:34 p.m. UTC 
These can be shared across EFI and non-EFI builds.

Signed-off-by: Varad Gautam <varad.gautam@suse.com>
---
 x86/cstart64.S | 60 +-----------------------------------------------
 x86/start32.S  | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 63 insertions(+), 59 deletions(-)
 create mode 100644 x86/start32.S

Comments

Sean Christopherson April 13, 2022, 7:33 p.m. UTC | #1 
On Tue, Apr 12, 2022, Varad Gautam wrote:
> These can be shared across EFI and non-EFI builds.
> 
> Signed-off-by: Varad Gautam <varad.gautam@suse.com>
> ---
> diff --git a/x86/start32.S b/x86/start32.S
> new file mode 100644
> index 0000000..9e00474
> --- /dev/null
> +++ b/x86/start32.S
> @@ -0,0 +1,62 @@
> +/* Common 32-bit code between EFI and non-EFI bootstrapping. */
> +
> +.code32
> +
> +MSR_GS_BASE = 0xc0000101
> +
> +.macro setup_percpu_area
> +	lea -4096(%esp), %eax
> +	mov $0, %edx
> +	mov $MSR_GS_BASE, %ecx
> +	wrmsr
> +.endm
> +
> +.macro setup_segments
> +	mov $MSR_GS_BASE, %ecx
> +	rdmsr
> +
> +	mov $0x10, %bx
> +	mov %bx, %ds
> +	mov %bx, %es
> +	mov %bx, %fs
> +	mov %bx, %gs
> +	mov %bx, %ss
> +
> +	/* restore MSR_GS_BASE */
> +	wrmsr
> +.endm
> +
> +prepare_64:
> +	lgdt gdt_descr
> +	setup_segments
> +
> +	xor %eax, %eax
> +	mov %eax, %cr4
> +
> +enter_long_mode:
> +	mov %cr4, %eax
> +	bts $5, %eax  // pae
> +	mov %eax, %cr4
> +
> +	mov pt_root, %eax
> +	mov %eax, %cr3
> +
> +efer = 0xc0000080
> +	mov $efer, %ecx
> +	rdmsr
> +	bts $8, %eax
> +	wrmsr
> +
> +	mov %cr0, %eax
> +	bts $0, %eax
> +	bts $31, %eax
> +	mov %eax, %cr0
> +	ret
> +
> +ap_start32:
> +	setup_segments
> +	mov $-4096, %esp
> +	lock xaddl %esp, smp_stacktop
> +	setup_percpu_area
> +	call prepare_64

I suspect this will conflict with my idea of using a dedicated percpu area.  But
can't that be remedied by adding a prep patch to drop setup_percpu_area and add a
C helper to the setup (using the dedicated area), called from ap_start64()?  I don't
see any instances of gs: being used before reset_apic().

Then the funky save/restore of MSR_GS_BASE also disappears.

> +	ljmpl $8, $ap_start64
> -- 
> 2.32.0
>
diff mbox series

Patch

diff --git a/x86/cstart64.S b/x86/cstart64.S
index 30012ca..6eb109d 100644
--- a/x86/cstart64.S
+++ b/x86/cstart64.S
@@ -56,35 +56,13 @@  mb_flags = 0x0
 	.long mb_magic, mb_flags, 0 - (mb_magic + mb_flags)
 mb_cmdline = 16
 
-MSR_GS_BASE = 0xc0000101
-
-.macro setup_percpu_area
-	lea -4096(%esp), %eax
-	mov $0, %edx
-	mov $MSR_GS_BASE, %ecx
-	wrmsr
-.endm
-
 .macro load_tss
 	movq %rsp, %rdi
 	call setup_tss
 	ltr %ax
 .endm
 
-.macro setup_segments
-	mov $MSR_GS_BASE, %ecx
-	rdmsr
-
-	mov $0x10, %bx
-	mov %bx, %ds
-	mov %bx, %es
-	mov %bx, %fs
-	mov %bx, %gs
-	mov %bx, %ss
-
-	/* restore MSR_GS_BASE */
-	wrmsr
-.endm
+#include "start32.S"
 
 .globl start
 start:
@@ -118,33 +96,6 @@  switch_to_5level:
 	call enter_long_mode
 	jmpl $8, $lvl5
 
-prepare_64:
-	lgdt gdt_descr
-	setup_segments
-
-	xor %eax, %eax
-	mov %eax, %cr4
-
-enter_long_mode:
-	mov %cr4, %eax
-	bts $5, %eax  // pae
-	mov %eax, %cr4
-
-	mov pt_root, %eax
-	mov %eax, %cr3
-
-efer = 0xc0000080
-	mov $efer, %ecx
-	rdmsr
-	bts $8, %eax
-	wrmsr
-
-	mov %cr0, %eax
-	bts $0, %eax
-	bts $31, %eax
-	mov %eax, %cr0
-	ret
-
 smp_stacktop:	.long stacktop - 4096
 
 .align 16
@@ -171,15 +122,6 @@  gdt32_descr:
 .globl sipi_end
 sipi_end:
 
-.code32
-ap_start32:
-	setup_segments
-	mov $-4096, %esp
-	lock xaddl %esp, smp_stacktop
-	setup_percpu_area
-	call prepare_64
-	ljmpl $8, $ap_start64
-
 .code64
 save_id:
 	movl $(APIC_DEFAULT_PHYS_BASE + APIC_ID), %eax
diff --git a/x86/start32.S b/x86/start32.S
new file mode 100644
index 0000000..9e00474
--- /dev/null
+++ b/x86/start32.S
@@ -0,0 +1,62 @@ 
+/* Common 32-bit code between EFI and non-EFI bootstrapping. */
+
+.code32
+
+MSR_GS_BASE = 0xc0000101
+
+.macro setup_percpu_area
+	lea -4096(%esp), %eax
+	mov $0, %edx
+	mov $MSR_GS_BASE, %ecx
+	wrmsr
+.endm
+
+.macro setup_segments
+	mov $MSR_GS_BASE, %ecx
+	rdmsr
+
+	mov $0x10, %bx
+	mov %bx, %ds
+	mov %bx, %es
+	mov %bx, %fs
+	mov %bx, %gs
+	mov %bx, %ss
+
+	/* restore MSR_GS_BASE */
+	wrmsr
+.endm
+
+prepare_64:
+	lgdt gdt_descr
+	setup_segments
+
+	xor %eax, %eax
+	mov %eax, %cr4
+
+enter_long_mode:
+	mov %cr4, %eax
+	bts $5, %eax  // pae
+	mov %eax, %cr4
+
+	mov pt_root, %eax
+	mov %eax, %cr3
+
+efer = 0xc0000080
+	mov $efer, %ecx
+	rdmsr
+	bts $8, %eax
+	wrmsr
+
+	mov %cr0, %eax
+	bts $0, %eax
+	bts $31, %eax
+	mov %eax, %cr0
+	ret
+
+ap_start32:
+	setup_segments
+	mov $-4096, %esp
+	lock xaddl %esp, smp_stacktop
+	setup_percpu_area
+	call prepare_64
+	ljmpl $8, $ap_start64