| Message ID | 20220624090828.62191-4-weijiang.yang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix up test failures due to recent KVM changes | expand |
On Fri, Jun 24, 2022, Yang Weijiang wrote: > Use new helper to check whether pmu is available and Perfmon/Debug > capbilities are supported before read MSR_IA32_PERF_CAPABILITIES to > avoid test failure. The issue can be captured when enable_pmu=0. > > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> > --- > lib/x86/processor.h | 2 +- > x86/pmu_lbr.c | 32 +++++++++++++------------------- > 2 files changed, 14 insertions(+), 20 deletions(-) > > diff --git a/lib/x86/processor.h b/lib/x86/processor.h > index 70b9193..bb917b0 100644 > --- a/lib/x86/processor.h > +++ b/lib/x86/processor.h > @@ -193,7 +193,7 @@ static inline bool is_intel(void) > #define X86_FEATURE_PAUSEFILTER (CPUID(0x8000000A, 0, EDX, 10)) > #define X86_FEATURE_PFTHRESHOLD (CPUID(0x8000000A, 0, EDX, 12)) > #define X86_FEATURE_VGIF (CPUID(0x8000000A, 0, EDX, 16)) > - > +#define X86_FEATURE_PDCM (CPUID(0x1, 0, ECX, 15)) Please try to think critically about the code you're writing. All of the existing X86_FEATURE_* definitions are organized by leaf, sub-leaf, register _and_ bit position. And now there's X86_FEATURE_PDCM...
On 6/25/2022 6:23 AM, Sean Christopherson wrote: > On Fri, Jun 24, 2022, Yang Weijiang wrote: >> Use new helper to check whether pmu is available and Perfmon/Debug >> capbilities are supported before read MSR_IA32_PERF_CAPABILITIES to >> avoid test failure. The issue can be captured when enable_pmu=0. >> >> Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> >> --- >> lib/x86/processor.h | 2 +- >> x86/pmu_lbr.c | 32 +++++++++++++------------------- >> 2 files changed, 14 insertions(+), 20 deletions(-) >> >> diff --git a/lib/x86/processor.h b/lib/x86/processor.h >> index 70b9193..bb917b0 100644 >> --- a/lib/x86/processor.h >> +++ b/lib/x86/processor.h >> @@ -193,7 +193,7 @@ static inline bool is_intel(void) >> #define X86_FEATURE_PAUSEFILTER (CPUID(0x8000000A, 0, EDX, 10)) >> #define X86_FEATURE_PFTHRESHOLD (CPUID(0x8000000A, 0, EDX, 12)) >> #define X86_FEATURE_VGIF (CPUID(0x8000000A, 0, EDX, 16)) >> - >> +#define X86_FEATURE_PDCM (CPUID(0x1, 0, ECX, 15)) > Please try to think critically about the code you're writing. All of the existing > X86_FEATURE_* definitions are organized by leaf, sub-leaf, register _and_ bit > position. And now there's X86_FEATURE_PDCM... My fault, will put it at the right place. thanks!
diff --git a/lib/x86/processor.h b/lib/x86/processor.h index 70b9193..bb917b0 100644 --- a/lib/x86/processor.h +++ b/lib/x86/processor.h @@ -193,7 +193,7 @@ static inline bool is_intel(void) #define X86_FEATURE_PAUSEFILTER (CPUID(0x8000000A, 0, EDX, 10)) #define X86_FEATURE_PFTHRESHOLD (CPUID(0x8000000A, 0, EDX, 12)) #define X86_FEATURE_VGIF (CPUID(0x8000000A, 0, EDX, 16)) - +#define X86_FEATURE_PDCM (CPUID(0x1, 0, ECX, 15)) static inline bool this_cpu_has(u64 feature) { diff --git a/x86/pmu_lbr.c b/x86/pmu_lbr.c index 688634d..497df1e 100644 --- a/x86/pmu_lbr.c +++ b/x86/pmu_lbr.c @@ -15,6 +15,7 @@ #define MSR_LBR_SELECT 0x000001c8 volatile int count; +u32 lbr_from, lbr_to; static noinline int compute_flag(int i) { @@ -38,18 +39,6 @@ static noinline int lbr_test(void) return 0; } -union cpuid10_eax { - struct { - unsigned int version_id:8; - unsigned int num_counters:8; - unsigned int bit_width:8; - unsigned int mask_length:8; - } split; - unsigned int full; -} eax; - -u32 lbr_from, lbr_to; - static void init_lbr(void *index) { wrmsr(lbr_from + *(int *) index, 0); @@ -63,7 +52,7 @@ static bool test_init_lbr_from_exception(u64 index) int main(int ac, char **av) { - struct cpuid id = cpuid(10); + u8 version = pmu_version(); u64 perf_cap; int max, i; @@ -74,19 +63,24 @@ int main(int ac, char **av) return 0; } - perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES); - eax.full = id.a; - - if (!eax.split.version_id) { + if (!version) { printf("No pmu is detected!\n"); return report_summary(); } + + if (!this_cpu_has(X86_FEATURE_PDCM)) { + printf("Perfmon/Debug Capabilities MSR isn't supported\n"); + return report_summary(); + } + + perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES); + if (!(perf_cap & PMU_CAP_LBR_FMT)) { - printf("No LBR is detected!\n"); + printf("(Architectural) LBR is not supported.\n"); return report_summary(); } - printf("PMU version: %d\n", eax.split.version_id); + printf("PMU version: %d\n", version); printf("LBR version: %ld\n", perf_cap & PMU_CAP_LBR_FMT); /* Look for LBR from and to MSRs */
Use new helper to check whether pmu is available and Perfmon/Debug capbilities are supported before read MSR_IA32_PERF_CAPABILITIES to avoid test failure. The issue can be captured when enable_pmu=0. Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> --- lib/x86/processor.h | 2 +- x86/pmu_lbr.c | 32 +++++++++++++------------------- 2 files changed, 14 insertions(+), 20 deletions(-)