From patchwork Thu Jul 21 18:12:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12925670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AF5CC43334 for ; Thu, 21 Jul 2022 18:12:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229591AbiGUSMb (ORCPT ); Thu, 21 Jul 2022 14:12:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229673AbiGUSM1 (ORCPT ); Thu, 21 Jul 2022 14:12:27 -0400 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 348653DF3A for ; Thu, 21 Jul 2022 11:12:26 -0700 (PDT) Received: by mail-pg1-x531.google.com with SMTP id f65so2335477pgc.12 for ; Thu, 21 Jul 2022 11:12:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JO4EgaFLA+7AeATY37WXQlGJ9vdJOA0mjTrTo1yHUWU=; b=riG2PtdLx0LlINs136KP5QyxDhqO+kVaZVCGH/J20pnAzCaWI0cNrw4ZKDVwIuQKzI s3DpyvOseHncIaaYhLOH8rx0kDgBjdmQ+VaSyFC5Te26GWSMTn/iDiwdMBSLbbySx1iz A/QtjMMVexwd7x+C6X+5Ka4WgCzL9oKKHK5fhduu7Y23VDfSJydWvcxzBlHNX0Y+JYow NlMMiIdZ8WTGaMGAdW+qWVbhP8ut+rKWjmzGrXNcbphrgxn9ziKf6TOmHxQcna3Xki3q g8zUDW456eefJqNCiXx4tF9aQ2VC3p4v6vcz4bF3Eb40szoNeVQvHZVgjCQsvw1DqLsg It4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JO4EgaFLA+7AeATY37WXQlGJ9vdJOA0mjTrTo1yHUWU=; b=jHaKdPldmJ/oUSqZgDm8YjiIDTs1q8jkPRqGxmoWGpZD57O6/FLqo9epSrNYdfyT/8 K0gl72f5CoxGjPHV29ORC4B+4yeA38qBlBnCx52Jvddd+zKJZXzvwSklgQx7Kdqb9U3y NW+NmNxK6A4+GKFeK6WjNCs4UiQXUBcWWfRXUruXN4Fh0pYik4Mm7XZUycXSmPeSgi66 odXMr7+B+dwSxBW8TSmzhxbzxtQFA1490CDbeildoMpD0iG7jo+f+Or4ZOpZyoLWpxA2 aBlVHvacccxyoOHUO7zdeUnArVLPgVT2Y2pQ6U7DZKln/XogqkpD97zldai9NxZKYQpD usIQ== X-Gm-Message-State: AJIora/P6+7o+pwoFq/irM3KuB7MMlqazGqncQmxLjgk+pjWwauln1Al hoBeWtKl8BWOA9SIPaPhA6X5NA== X-Google-Smtp-Source: AGRyM1vCz2MPQ+o0CTmBQcVDehcx5aKC828ghajOSEd6ubFHv0tSkQh5zBLbLycgTGSqipKoq1bssQ== X-Received: by 2002:a63:ff4c:0:b0:412:b100:786b with SMTP id s12-20020a63ff4c000000b00412b100786bmr39952104pgk.537.1658427145703; Thu, 21 Jul 2022 11:12:25 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id b12-20020a1709027e0c00b0016d3a354cffsm617358plm.89.2022.07.21.11.12.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 11:12:25 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Albert Ou , Atish Patra , Daniel Lezcano , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Thomas Gleixner , Tsukasa OI , Wei Fu Subject: [PATCH v6 2/4] RISC-V: Enable sstc extension parsing from DT Date: Thu, 21 Jul 2022 11:12:10 -0700 Message-Id: <20220721181212.3705138-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220721181212.3705138-1-atishp@rivosinc.com> References: <20220721181212.3705138-1-atishp@rivosinc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The ISA extension framework now allows parsing any multi-letter ISA extension. Enable that for sstc extension. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 4e2486881840..b186fff75198 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -53,6 +53,7 @@ extern unsigned long elf_hwcap; enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_SVPBMT, + RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index fba9e9f46a8c..0016d9337fe0 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -89,6 +89,7 @@ int riscv_of_parent_hartid(struct device_node *node) static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 12b05ce164bb..034bdbd189d0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -199,6 +199,7 @@ void __init riscv_fill_hwcap(void) } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); + SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); } #undef SET_ISA_EXT_MAP }