From patchwork Wed Aug 31 22:34:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yang, Weijiang" X-Patchwork-Id: 12961647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50866ECAAD4 for ; Thu, 1 Sep 2022 01:37:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232789AbiIABhT (ORCPT ); Wed, 31 Aug 2022 21:37:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232698AbiIABhJ (ORCPT ); Wed, 31 Aug 2022 21:37:09 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63DCC15A23E; Wed, 31 Aug 2022 18:37:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661996226; x=1693532226; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tXSUqw/inUg+rHmV9OisbAEhnPZvWwokhVXEgZHxmdo=; b=ZrlyG1jONj2hef9QkAh/iCskghkda/boVGtgab+dmx+MMrzyIR4+nbuM cqMB1QIACk+Ot2rsIR5ocNxsVgsYaiHKQC2GEwYiBljfgygAzZdMTu0it ROBM0lwc/yiafIdyp+hWyVTo+lwzjljOznqHubJ5LakTp1AirnCdnLlHh R6SnSWeOPti2GF8lZTk0ugU9kyqLSLEZxe970Jy2T3DAnwt4va3xqjOLX Bxc0gRuWtN8qviyDN61jEEC5+ytpVOGCiD9jFJhhd+JVZlM2NUEEb20rZ b/UfVJw17ylVawBeTyYDGMnwR64cLr4f+5dUK02PcHHcPWeEJMzQ7uAqW w==; X-IronPort-AV: E=McAfee;i="6500,9779,10456"; a="321735083" X-IronPort-AV: E=Sophos;i="5.93,279,1654585200"; d="scan'208";a="321735083" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 18:37:01 -0700 X-IronPort-AV: E=Sophos;i="5.93,279,1654585200"; d="scan'208";a="754625995" Received: from embargo.jf.intel.com ([10.165.9.183]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 18:37:01 -0700 From: Yang Weijiang To: pbonzini@redhat.com, seanjc@google.com, kvm@vger.kernel.org Cc: like.xu.linux@gmail.com, kan.liang@linux.intel.com, wei.w.wang@intel.com, linux-kernel@vger.kernel.org Subject: [PATCH 06/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL for guest Arch LBR Date: Wed, 31 Aug 2022 18:34:29 -0400 Message-Id: <20220831223438.413090-7-weijiang.yang@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220831223438.413090-1-weijiang.yang@intel.com> References: <20220831223438.413090-1-weijiang.yang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Paolo Bonzini Arch LBR is enabled by setting MSR_ARCH_LBR_CTL.LBREn to 1. A new guest state field named "Guest IA32_LBR_CTL" is added to enhance guest LBR usage. When guest Arch LBR is enabled, a guest LBR event will be created like the model-specific LBR does. Clear guest LBR enable bit on host PMI handling so guest can see expected config. On processors that support Arch LBR, MSR_IA32_DEBUGCTLMSR[bit 0] has no meaning. It can be written to 0 or 1, but reads will always return 0. Like IA32_DEBUGCTL, IA32_ARCH_LBR_CTL msr is also preserved on INIT. Regardless of the Arch LBR or legacy LBR, when the LBR_EN bit 0 of the corresponding control MSR is set to 1, LBR recording will be enabled. Signed-off-by: Like Xu Co-developed-by: Yang Weijiang Signed-off-by: Yang Weijiang Reviewed-by: Kan Liang Message-Id: <20220517154100.29983-8-weijiang.yang@intel.com> Signed-off-by: Paolo Bonzini --- arch/x86/events/intel/lbr.c | 2 - arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/vmx.h | 2 + arch/x86/kvm/vmx/pmu_intel.c | 67 ++++++++++++++++++++++++++++---- arch/x86/kvm/vmx/vmx.c | 7 ++++ 5 files changed, 69 insertions(+), 10 deletions(-) diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 4ed6d3691e10..1d2c83c3644f 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -160,8 +160,6 @@ enum { ARCH_LBR_RETURN |\ ARCH_LBR_OTHER_BRANCH) -#define ARCH_LBR_CTL_MASK 0x7f000e - static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc); static __always_inline bool is_lbr_call_stack_bit_set(u64 config) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 6674bdb096f3..5508ff3f1bd6 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -215,6 +215,7 @@ #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) #define MSR_ARCH_LBR_CTL 0x000014ce +#define ARCH_LBR_CTL_MASK 0x7f000e #define ARCH_LBR_CTL_LBREN BIT(0) #define ARCH_LBR_CTL_CPL_OFFSET 1 #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index c371ef695fcc..50c6f36daaea 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -257,6 +257,8 @@ enum vmcs_field { GUEST_BNDCFGS_HIGH = 0x00002813, GUEST_IA32_RTIT_CTL = 0x00002814, GUEST_IA32_RTIT_CTL_HIGH = 0x00002815, + GUEST_IA32_LBR_CTL = 0x00002816, + GUEST_IA32_LBR_CTL_HIGH = 0x00002817, HOST_IA32_PAT = 0x00002c00, HOST_IA32_PAT_HIGH = 0x00002c01, HOST_IA32_EFER = 0x00002c02, diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index eb35cf2845ca..e06de1f29fe7 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -19,6 +19,7 @@ #include "pmu.h" #define MSR_PMC_FULL_WIDTH_BIT (MSR_IA32_PMC0 - MSR_IA32_PERFCTR0) +#define KVM_ARCH_LBR_CTL_MASK (ARCH_LBR_CTL_MASK | ARCH_LBR_CTL_LBREN) static struct kvm_event_hw_type_mapping intel_arch_events[] = { [0] = { 0x3c, 0x00, PERF_COUNT_HW_CPU_CYCLES }, @@ -182,7 +183,7 @@ static bool intel_pmu_is_valid_lbr_msr(struct kvm_vcpu *vcpu, u32 index) (index == MSR_LBR_SELECT || index == MSR_LBR_TOS)) return true; - if (index == MSR_ARCH_LBR_DEPTH) + if (index == MSR_ARCH_LBR_DEPTH || index == MSR_ARCH_LBR_CTL) return kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR) && guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR); @@ -349,6 +350,30 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu, return true; } +static bool arch_lbr_ctl_is_valid(struct kvm_vcpu *vcpu, u64 ctl) +{ + struct kvm_cpuid_entry2 *entry; + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + + if (!pmu->kvm_arch_lbr_depth) + return false; + + if (ctl & ~KVM_ARCH_LBR_CTL_MASK) + return false; + + entry = kvm_find_cpuid_entry(vcpu, 0x1c); + if (!entry) + return false; + + if (!(entry->ebx & BIT(0)) && (ctl & ARCH_LBR_CTL_CPL)) + return false; + if (!(entry->ebx & BIT(2)) && (ctl & ARCH_LBR_CTL_STACK)) + return false; + if (!(entry->ebx & BIT(1)) && (ctl & ARCH_LBR_CTL_FILTER)) + return false; + return true; +} + static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -381,6 +406,14 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_ARCH_LBR_DEPTH: msr_info->data = lbr_desc->records.nr; return 0; + case MSR_ARCH_LBR_CTL: + if (!kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR)) { + WARN_ON_ONCE(!msr_info->host_initiated); + msr_info->data = 0; + } else { + msr_info->data = vmcs_read64(GUEST_IA32_LBR_CTL); + } + return 0; default: if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { @@ -483,6 +516,18 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) if (kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR)) wrmsrl(MSR_ARCH_LBR_DEPTH, lbr_desc->records.nr); return 0; + case MSR_ARCH_LBR_CTL: + if (msr_info->host_initiated && !pmu->kvm_arch_lbr_depth) + return data != 0; + + if (!arch_lbr_ctl_is_valid(vcpu, data)) + break; + + vmcs_write64(GUEST_IA32_LBR_CTL, data); + if (intel_pmu_lbr_is_enabled(vcpu) && !lbr_desc->event && + (data & ARCH_LBR_CTL_LBREN)) + intel_pmu_create_guest_lbr_event(vcpu); + return 0; default: if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { @@ -729,12 +774,16 @@ static void intel_pmu_reset(struct kvm_vcpu *vcpu) */ static void intel_pmu_legacy_freezing_lbrs_on_pmi(struct kvm_vcpu *vcpu) { - u64 data = vmcs_read64(GUEST_IA32_DEBUGCTL); + u32 lbr_ctl_field = GUEST_IA32_DEBUGCTL; - if (data & DEBUGCTLMSR_FREEZE_LBRS_ON_PMI) { - data &= ~DEBUGCTLMSR_LBR; - vmcs_write64(GUEST_IA32_DEBUGCTL, data); - } + if (!(vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_FREEZE_LBRS_ON_PMI)) + return; + + if (kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR) && + guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR)) + lbr_ctl_field = GUEST_IA32_LBR_CTL; + + vmcs_write64(lbr_ctl_field, vmcs_read64(lbr_ctl_field) & ~0x1ULL); } static void intel_pmu_deliver_pmi(struct kvm_vcpu *vcpu) @@ -803,7 +852,8 @@ void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); - bool lbr_enable = !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR) && + bool lbr_enable = guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR) ? + (vmcs_read64(GUEST_IA32_LBR_CTL) & ARCH_LBR_CTL_LBREN) : (vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR); if (!lbr_desc->event) { @@ -831,7 +881,8 @@ void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu) static void intel_pmu_cleanup(struct kvm_vcpu *vcpu) { - bool lbr_enable = !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR) && + bool lbr_enable = guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR) ? + (vmcs_read64(GUEST_IA32_LBR_CTL) & ARCH_LBR_CTL_LBREN) : (vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR); if (!lbr_enable) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index c9b49a09e6b5..020db207215b 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -2104,6 +2104,13 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) VM_EXIT_SAVE_DEBUG_CONTROLS) get_vmcs12(vcpu)->guest_ia32_debugctl = data; + /* + * For Arch LBR, IA32_DEBUGCTL[bit 0] has no meaning. + * It can be written to 0 or 1, but reads will always return 0. + */ + if (guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR)) + data &= ~DEBUGCTLMSR_LBR; + vmcs_write64(GUEST_IA32_DEBUGCTL, data); if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event && (data & DEBUGCTLMSR_LBR))