From patchwork Thu Nov 17 09:19:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suleiman Souhlal X-Patchwork-Id: 13046389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08DEDC433FE for ; Thu, 17 Nov 2022 09:22:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239881AbiKQJWT (ORCPT ); Thu, 17 Nov 2022 04:22:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239987AbiKQJV6 (ORCPT ); Thu, 17 Nov 2022 04:21:58 -0500 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45169697DB for ; Thu, 17 Nov 2022 01:21:55 -0800 (PST) Received: by mail-yb1-xb49.google.com with SMTP id 204-20020a2510d5000000b006be7970889cso1008889ybq.21 for ; Thu, 17 Nov 2022 01:21:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=raaoQl8+LtvkCitEgdlnV5Yakk/YJIPWXn+n/iuEH/0=; b=fi/hzvFs59YPiGrjI9zGZca93SjbnRsGoxh/a80IV+8NnXhuII2xUyTsqnZGmY18Le /bd8nIKdw82iuiQa1Uy2m5moEKxWLas/VDCewDSZOmO01o/mp0ca4Chbn/q27EMCIBlf oc9atufgM8PxvkjNsNEG4VJMx64nQmQG/xXa+ji/S8S9hUyj2cian0EtR8SsHSqiVk8t r6+FDMbvSiIHv3NsyBQB0ZDIdfmJYGIonRtDuDgGb+ozmccl6ykU7rSlg3K9rzhCVeGe im2CP+n8a5Yh4LpFk9qW+x+Tazuz0HdkWY7oVX6zcCUZHxf9AwzdOBNgwoCt8EfP4Fj3 HBMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=raaoQl8+LtvkCitEgdlnV5Yakk/YJIPWXn+n/iuEH/0=; b=3fGEFrpdagBikztlhZyXu/OzokJg+21Wyyy6eUrhLxVuQd2tHiC1T2tcnJIEu6Jzs/ qeuDm3fdjr9ENkBiL6GTysgpPNEo/pn78PKxbfyYNowDM1L0RwHy3AX8v9REPyGUOF73 p77zlZLvhkwnskFPOxbRKqt2SaII1LTuErqj43flJPbNpNgoqXz/BtMPNyzUXst/E5b4 R3AaKBZq1zQpaSMhbLmdHAoQEGUCe1cmExF8SL7TQGEEs3tTGL5mS+6CW2YPbc7K9s9j pkHuu5FfZMNqgqhj9Da6Nwb85CMqz74n2EGhCwPsyOyDpNts68s0vmFBNYqXsLZENEqS AuiA== X-Gm-Message-State: ANoB5pmbUJ0FridpawICXfxycFVUNAsOfU3BRftsCr1NOfPjPgfzhClG ptXBXlr3LZvTg4psstdgMY+DaksMIFT62g== X-Google-Smtp-Source: AA0mqf6PUvDIzftu71kikd5IdNb930uWxI8E0A+xVqsWq2tzAQiNR2/MZapSCb7XaiDlBwxo/sMcXcvSpy+9Qg== X-Received: from suleiman1.tok.corp.google.com ([2401:fa00:8f:203:416e:f3c7:7f1d:6e]) (user=suleiman job=sendgmr) by 2002:a5b:285:0:b0:6d3:bab1:8d32 with SMTP id x5-20020a5b0285000000b006d3bab18d32mr1255065ybl.541.1668676914593; Thu, 17 Nov 2022 01:21:54 -0800 (PST) Date: Thu, 17 Nov 2022 18:19:42 +0900 In-Reply-To: <20221117091952.1940850-1-suleiman@google.com> Message-Id: <20221117091952.1940850-25-suleiman@google.com> Mime-Version: 1.0 References: <20221117091952.1940850-1-suleiman@google.com> X-Mailer: git-send-email 2.38.1.431.g37b22c650d-goog Subject: [PATCH 4.19 24/34] x86/speculation: Remove x86_spec_ctrl_mask From: Suleiman Souhlal To: stable@vger.kernel.org Cc: x86@kernel.org, kvm@vger.kernel.org, bp@alien8.de, pbonzini@redhat.com, peterz@infradead.org, jpoimboe@kernel.org, cascardo@canonical.com, surajjs@amazon.com, ssouhlal@FreeBSD.org, suleiman@google.com Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Josh Poimboeuf commit acac5e98ef8d638a411cfa2ee676c87e1973f126 upstream. This mask has been made redundant by kvm_spec_ctrl_test_value(). And it doesn't even work when MSR interception is disabled, as the guest can just write to SPEC_CTRL directly. Signed-off-by: Josh Poimboeuf Signed-off-by: Borislav Petkov Reviewed-by: Paolo Bonzini Signed-off-by: Borislav Petkov Signed-off-by: Thadeu Lima de Souza Cascardo Signed-off-by: Greg Kroah-Hartman Signed-off-by: Suleiman Souhlal --- arch/x86/kernel/cpu/bugs.c | 31 +------------------------------ 1 file changed, 1 insertion(+), 30 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 8ab96965bf28..95d8b517cf4d 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -83,12 +83,6 @@ u64 spec_ctrl_current(void) } EXPORT_SYMBOL_GPL(spec_ctrl_current); -/* - * The vendor and possibly platform specific bits which can be modified in - * x86_spec_ctrl_base. - */ -static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; - /* * AMD specific MSR info for Speculative Store Bypass control. * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). @@ -137,10 +131,6 @@ void __init check_bugs(void) if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); - /* Allow STIBP in MSR_SPEC_CTRL if supported */ - if (boot_cpu_has(X86_FEATURE_STIBP)) - x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; - /* Select the proper CPU mitigations before patching alternatives: */ spectre_v1_select_mitigation(); spectre_v2_select_mitigation(); @@ -198,19 +188,10 @@ void __init check_bugs(void) void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) { - u64 msrval, guestval, hostval = spec_ctrl_current(); + u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current(); struct thread_info *ti = current_thread_info(); - /* Is MSR_SPEC_CTRL implemented ? */ if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { - /* - * Restrict guest_spec_ctrl to supported values. Clear the - * modifiable bits in the host base value and or the - * modifiable bits from the guest value. - */ - guestval = hostval & ~x86_spec_ctrl_mask; - guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; - if (hostval != guestval) { msrval = setguest ? guestval : hostval; wrmsrl(MSR_IA32_SPEC_CTRL, msrval); @@ -1542,16 +1523,6 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void) break; } - /* - * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper - * bit in the mask to allow guests to use the mitigation even in the - * case where the host does not enable it. - */ - if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || - static_cpu_has(X86_FEATURE_AMD_SSBD)) { - x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; - } - /* * We have three CPU feature flags that are in play here: * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.