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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , "Konrad Rzeszutek Wilk" , Paolo Bonzini , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , Alexey Kardashevskiy , , , Subject: [PATCH v3 1/7] x86/cpu, kvm: Define a scattered No Nested Data Breakpoints feature bit Date: Tue, 29 Nov 2022 17:58:10 -0600 Message-ID: <20221129235816.188737-2-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221129235816.188737-1-kim.phillips@amd.com> References: <20221129235816.188737-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT089:EE_|SA0PR12MB4496:EE_ X-MS-Office365-Filtering-Correlation-Id: 868e6511-5d51-4477-c9c2-08dad265a6a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: x/CzIxxiBcUXtOORtPtXQYMHsKMDVQkvQcjditKtJRTonA+uJ2yqx1eQdfpE01pQ57o6xuOOG2Mn8K37aZhDtq2K52AUiaCJc7Ksn3d5RKW9IusvLeXFBo7mbucXQrgTiy6Y6jmOmzqEL9YsMfqhdO9ZbKtQzuhV9/7ICfIa9DxevJhuuwXWybL5qVQd1V3EsUivhVywZdeK0AY0SXsH25Hlcs0cS4u6AO/c8zzV6iSBdp4Qg61puVSkpQyqOJ7qw+zyiIZY7JzTpLiBH6LF3ZqAwYj4gievgOgqQYRyPYWZq/MpIITdbKxlu7t9FyRq8H3k5PcumNEazQLlFKjxL06dOsmo4t/zsuryVfil7nK0lXb8yAsQDI7HJFlxYsGOU+qIP5xcUW4RzS8KNKldEcekKxRIpeNjQNTDOhytKIsuSr+nI8kHsZzefFwLuCpplh6u0K6R/QwAIg/5M43eeJd8RT5uFySmpmWcj8Br71wXJ/3spVc37DLgKNZ1ov7nZpQHDi1B9keaH9aP6bIUW3PYTtD1rc3cpeZPyaAZFUZn60XcuAJfSqbtQLPgG3X9pJrpSOKD73DIUItXX6wiZd1v4i2KcBd3L/SUj8uB9rud94KzozMZZjH1pCeQrZWggHTSi1EPD3fqVrxkUFBECGWLpgiLj3mHVWIsrtudZGNm++2BySFT7T3ps0hYiCOwDEEAaU5/dfNmzdbPXnpWYgXMkkmpZNVLhdtr1LSifOI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(346002)(396003)(136003)(451199015)(40470700004)(36840700001)(46966006)(478600001)(70586007)(316002)(2906002)(70206006)(6916009)(36756003)(54906003)(356005)(81166007)(40460700003)(82740400003)(426003)(83380400001)(6666004)(47076005)(36860700001)(82310400005)(40480700001)(26005)(86362001)(336012)(16526019)(2616005)(186003)(7696005)(1076003)(44832011)(7416002)(5660300002)(41300700001)(8936002)(4326008)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2022 23:58:45.4912 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 868e6511-5d51-4477-c9c2-08dad265a6a4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4496 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org It's a part of the CPUID 0x80000021 leaf, and this allows us to group this and other CPUID 0x80000021 EAX feature bits to being propagated via kvm_set_cpu_caps instead of open-coding them in __do_cpuid_func(). Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b6525491a41b..b16fdcedc2b5 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -306,8 +306,8 @@ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */ #define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX EDECCSSA user leaf function */ #define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */ - #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */ +#define X86_FEATURE_NO_NESTED_DATA_BP (11*32+21) /* "" AMD No Nested Data Breakpoints */ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index f53944fb8f7f..079e253e1049 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, + { X86_FEATURE_NO_NESTED_DATA_BP,CPUID_EAX, 0, 0x80000021, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { 0, 0, 0, 0, 0 }