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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , "Konrad Rzeszutek Wilk" , Paolo Bonzini , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , Alexey Kardashevskiy , , , Subject: [PATCH v3 5/7] x86/cpu, kvm: Define a scattered AMD Automatic IBRS feature bit Date: Tue, 29 Nov 2022 17:58:14 -0600 Message-ID: <20221129235816.188737-6-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221129235816.188737-1-kim.phillips@amd.com> References: <20221129235816.188737-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT099:EE_|BL3PR12MB6378:EE_ X-MS-Office365-Filtering-Correlation-Id: d82324d0-d1a7-4d73-dedb-08dad265c224 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hEcpmisT44hghpM4hsEuuu+TQAGMTvuqXhCTnfES7ZFfc0UD4jftyeb0fU9kcMD94ok7exH72V9DaVnZbNA5i8ggDWamtp6dAbnfC1Ah85uEnLXw/5SH7Dg3FMDsE5VAZmgfYYmGFtE4Mxq0DbEnZ5b/S64BouqG1dWDT/hRHcPQNhx2v91ws8oAzUsaT6Cg7piL4l1DUGak5nFOWS2KM+3tHdgqM0+p8+wvw3m4zd8yG3ACzL1IeKd6OR8NAPU4OKch5bd5jRBClUW3E95FVjpJ5SDdvs9ejJN6C8AkA8sw+LXbeXRJmn1E0cowoVbivnrHVPtPCqW85HZXRoTbrg+Y/siXvQOFO45ytgSA0ZvEF2hOkDqC185S06q/JSxY4S7NELWoz8kruMp+C70PDQScbgDWC/BPNrG84gmuy+Vnjj9s/cQjN7t2Jqi+PAOMKKGqG8zUaawX8uBbZbGFXzzGUbJua5e1tsoGb+pJj9/ccXVvNeL7l+yD7DXCXq0UYOUTedFefBTbpNYdIvJj7/YRYQKSJV9J+6R2HU3+u3QE7KRPOPaGs9HJ8VuBBQi5WnmwhkdakiyxGwoZsn4GlOgUpFIreFtNvXl0DYLvYuIitf7lsQhhHnkuvBxbzIsXvaRfS+cj7+3kpajEJmbVuL6z3/oxS+PqVYDUNxqtKdnc8aBOZXeJHLs1+8IVQjHTArZ/ZgY8FIaU6MXyGOSBueq1FwKgHugD0SqQ9OWHpV8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(136003)(396003)(39860400002)(376002)(451199015)(36840700001)(40470700004)(46966006)(41300700001)(478600001)(36756003)(7696005)(36860700001)(336012)(316002)(54906003)(6666004)(356005)(4326008)(8676002)(82740400003)(70206006)(26005)(70586007)(82310400005)(8936002)(2906002)(186003)(44832011)(1076003)(2616005)(5660300002)(7416002)(16526019)(86362001)(40460700003)(40480700001)(81166007)(6916009)(47076005)(426003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2022 23:59:31.6291 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d82324d0-d1a7-4d73-dedb-08dad265c224 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT099.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6378 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org It's a part of the CPUID 0x80000021 leaf, and this allows us to group this and other CPUID 0x80000021 EAX feature bits to being propagated via kvm_set_cpu_caps instead of open-coding them in __do_cpuid_func(). Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 5ddde18c1ae8..961eb49532b7 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -309,6 +309,7 @@ #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */ #define X86_FEATURE_NO_NESTED_DATA_BP (11*32+21) /* "" AMD No Nested Data Breakpoints */ #define X86_FEATURE_NULL_SEL_CLR_BASE (11*32+22) /* "" AMD Null Selector Clears Base */ +#define X86_FEATURE_AUTOIBRS (11*32+23) /* AMD Automatic IBRS */ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index caa03466cd9e..7ae7203cd410 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -48,6 +48,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_NO_NESTED_DATA_BP,CPUID_EAX, 0, 0x80000021, 0 }, { X86_FEATURE_LFENCE_RDTSC, CPUID_EAX, 2, 0x80000021, 0 }, { X86_FEATURE_NULL_SEL_CLR_BASE,CPUID_EAX, 6, 0x80000021, 0 }, + { X86_FEATURE_AUTOIBRS, CPUID_EAX, 8, 0x80000021, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { 0, 0, 0, 0, 0 }