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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , "Konrad Rzeszutek Wilk" , Paolo Bonzini , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , Alexey Kardashevskiy , , , Subject: [PATCH v4 2/7] x86/cpu: Define a scattered Null Selector Clears Base feature bit Date: Wed, 30 Nov 2022 19:49:58 -0600 Message-ID: <20221201015003.295769-3-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221201015003.295769-1-kim.phillips@amd.com> References: <20221201015003.295769-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0000EE3F:EE_|PH7PR12MB7426:EE_ X-MS-Office365-Filtering-Correlation-Id: 495e7954-cfcd-4868-10ab-08dad33e748e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QvEhnC96ob7c4cb1TSlcnhg+kRm6UBDPfe15ch7dqYzGyJM58/GM78DhstwfIUqv8WVxtaWmaPS3TYLC+edZ3mW2OwjAkTvHXal4h6edSy12Q9rvVoPuQnF5DcLw3XI+ncVa68ZlU1DqSgLxOwr2SKkaMdymnIoXifKXODktLozGDQsQpBfTyKlA8oxOr6lMhPDcUZ0nJNvQYiw6ldz3dovB2eznT4ZgYwtYuS3NRjRoWACLya1rC5m9YLWxScj8tOPE1wmageESsEHuYXQW1/BEsWus4KedThiClNP9tFoVaXguRqcnYiBOiCbAYl32mCEQ/k1W50KUsntN3eEOnEw+E8S0afvhAPY9gFsj4y0OLkoBSoA2OV8Ww7KuZBsEqD3RVl0vn2cmm/qDByK1CjSAHasxHwn3iiRZyN0Dd02CB0WCqfO6PD6zInqBl31X7RmJj8QTI30+FmpXTNI//5MLCF4V5yvhallIaS/tZu/t+UNwyeZvQjMGW9f5uW/N8zeHT7qXvA4usZ12lUBuPFUqeei2yDQbf70iZGBqjdKcPyQmSumsIk5mKK9JEYrHKUbK+XFSKNzg6EYiHcpvWZgY4bJfhmCm2fNPn/K1sQXScDvF53Gl3o+P2Epg4EjR0PN5ga1b2SyMcHQSbG8IOQnlNSLQw3pE489TD/KPuNFux1xj0LXCwWQXBnSConQI1K11W+fVhVhSZKdcJPZtobNaJT6mqNtjKZF100PGEkY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(376002)(346002)(136003)(451199015)(46966006)(40470700004)(36840700001)(7416002)(7696005)(5660300002)(1076003)(6666004)(4326008)(478600001)(83380400001)(70206006)(8936002)(2616005)(70586007)(186003)(47076005)(336012)(16526019)(8676002)(36860700001)(426003)(44832011)(2906002)(41300700001)(82740400003)(86362001)(82310400005)(26005)(316002)(54906003)(6916009)(36756003)(40460700003)(40480700001)(81166007)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2022 01:50:42.2621 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 495e7954-cfcd-4868-10ab-08dad33e748e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000EE3F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7426 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org It's a part of the CPUID 0x80000021 leaf, and this allows us to group this and other CPUID 0x80000021 EAX feature bits to being propagated via kvm_set_cpu_caps() instead of open-coding them in __do_cpuid_func(). Also use the feature bit definition in check_null_seg_clears_base() instead of open-coding it. Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/common.c | 3 +-- arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b16fdcedc2b5..5ddde18c1ae8 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ #define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */ #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */ #define X86_FEATURE_NO_NESTED_DATA_BP (11*32+21) /* "" AMD No Nested Data Breakpoints */ +#define X86_FEATURE_NULL_SEL_CLR_BASE (11*32+22) /* "" AMD Null Selector Clears Base */ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 73cc546e024d..8d28cd7c9072 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1683,8 +1683,7 @@ void check_null_seg_clears_base(struct cpuinfo_x86 *c) return; /* Zen3 CPUs advertise Null Selector Clears Base in CPUID. */ - if (c->extended_cpuid_level >= 0x80000021 && - cpuid_eax(0x80000021) & BIT(6)) + if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE)) return; /* diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 079e253e1049..d0734cc19d37 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -46,6 +46,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_NO_NESTED_DATA_BP,CPUID_EAX, 0, 0x80000021, 0 }, + { X86_FEATURE_NULL_SEL_CLR_BASE,CPUID_EAX, 6, 0x80000021, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { 0, 0, 0, 0, 0 }