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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , "Konrad Rzeszutek Wilk" , Paolo Bonzini , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , Alexey Kardashevskiy , , , Subject: [PATCH v4 7/7] x86/cpu, kvm: Propagate the AMD Automatic IBRS feature to the guest Date: Wed, 30 Nov 2022 19:50:03 -0600 Message-ID: <20221201015003.295769-8-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221201015003.295769-1-kim.phillips@amd.com> References: <20221201015003.295769-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT094:EE_|DM6PR12MB4188:EE_ X-MS-Office365-Filtering-Correlation-Id: 7d9001e8-fd08-4790-6bfc-08dad33ea176 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ILfn7DiucaIT4zbpN12X2zbbMeYqdM1z0nHVhHfGpaPN+lWLDgoYqWdAIxU11RRdppFOvFFwbFf3yfr8hKENlqxNmuRJUUIxbw21H2fTwFPMu3aoxxULSGF3ToCOVHR3vWTNbyDpzemIGRfVWVVY4tViMFOF6sMFPFcGCY/UsTjsdCZM4AoNHnGMWeNYWqQXUba/gLLAJvXMmCjenLxDr8dYEr3Dzmw2mRBnlBm0nhb08FlLLe5cEpHBLPI8hQ6wcrQv53uZxwngegqjxY2yciBsNX/ttqYAkvUyuVhFpQFm0aIzBkzHsjY1i1pkfGuSqzImGQ+Z761IgSwv3/BMMxgstcplp1v/r6axM8raVMAGfW1i7JkUPYBrOBr48L9p1xaZOTf9h8ZvlK0p0z024z2aZXfATaQ7LPBqZkyjsCEiWOZCQoBOHNL0a4PCErqBnbV6aFnvIveKb1l9N1Du3ZQtXH3MsSNMAqKYgdUhSknE1fyNdT/9m1RMCXh9jBVXU/RuGk0Biy05neIU1Hm0t8AagY+Q6ANep62vcBupGe4P8ekF2SNVTHV1r3k8GA/sxQco2h8P0rcDyfIpc3YkCForhPs0/xggj8JWU+a1qn58Rt+/+cXGUMvLmyLbaz7c+xSJNk07XyVcDsqy5+3hB0K33QdkBPhOupdMt+jg9dm86qQG0+zq+KY0bJX1vTWUHN9UlH/6wB47gkI8FzdQ3d9SEUUGqCLlsM1UgSW56b8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(396003)(136003)(346002)(451199015)(40470700004)(46966006)(36840700001)(316002)(70586007)(478600001)(1076003)(70206006)(2906002)(40460700003)(81166007)(356005)(54906003)(36756003)(82740400003)(83380400001)(426003)(47076005)(26005)(6666004)(82310400005)(40480700001)(16526019)(2616005)(86362001)(336012)(36860700001)(7696005)(186003)(6916009)(7416002)(44832011)(5660300002)(41300700001)(8936002)(4326008)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2022 01:51:57.6203 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7d9001e8-fd08-4790-6bfc-08dad33ea176 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT094.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4188 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add the AMD Automatic IBRS feature bit to those being propagated to the guest, and enable the guest EFER bit. Signed-off-by: Kim Phillips --- arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/reverse_cpuid.h | 2 ++ arch/x86/kvm/svm/svm.c | 3 +++ arch/x86/kvm/x86.c | 3 +++ 4 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index dd0fe79521eb..0ed3ad3e9341 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -732,7 +732,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_init_scattered(CPUID_8000_0021_EAX, SF(NO_NESTED_DATA_BP) | SF(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | - SF(NULL_SEL_CLR_BASE) | 0 /* PrefetchCtlMsr */ + SF(NULL_SEL_CLR_BASE) | SF(AUTOIBRS) | 0 /* PrefetchCtlMsr */ ); if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index 184614e27d5b..0bf02c02bb0a 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -30,6 +30,7 @@ enum kvm_only_cpuid_leafs { #define KVM_X86_FEATURE_NO_NESTED_DATA_BP KVM_X86_FEATURE(CPUID_8000_0021_EAX, 0) #define KVM_X86_FEATURE_LFENCE_RDTSC KVM_X86_FEATURE(CPUID_8000_0021_EAX, 2) #define KVM_X86_FEATURE_NULL_SEL_CLR_BASE KVM_X86_FEATURE(CPUID_8000_0021_EAX, 6) +#define KVM_X86_FEATURE_AUTOIBRS KVM_X86_FEATURE(CPUID_8000_0021_EAX, 8) struct cpuid_reg { u32 function; @@ -89,6 +90,7 @@ static __always_inline u32 __feature_translate(int x86_feature) case X86_FEATURE_NO_NESTED_DATA_BP: return KVM_X86_FEATURE_NO_NESTED_DATA_BP; case X86_FEATURE_LFENCE_RDTSC: return KVM_X86_FEATURE_LFENCE_RDTSC; case X86_FEATURE_NULL_SEL_CLR_BASE: return KVM_X86_FEATURE_NULL_SEL_CLR_BASE; + case X86_FEATURE_AUTOIBRS: return KVM_X86_FEATURE_AUTOIBRS; default: break; } diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 4b6d2b050e57..3ac3d4cfce24 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4960,6 +4960,9 @@ static __init int svm_hardware_setup(void) tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX); + if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) + kvm_enable_efer_bits(EFER_AUTOIBRS); + /* Check for pause filtering support */ if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { pause_filter_count = 0; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 490ec23c8450..db0f522fd597 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1682,6 +1682,9 @@ static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) { + if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS)) + return false; + if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) return false;