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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , "Konrad Rzeszutek Wilk" , Paolo Bonzini , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , Alexey Kardashevskiy , , , Subject: [PATCH v5 7/7] x86/cpu, kvm: Propagate the AMD Automatic IBRS feature to the guest Date: Mon, 5 Dec 2022 17:32:35 -0600 Message-ID: <20221205233235.622491-8-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221205233235.622491-1-kim.phillips@amd.com> References: <20221205233235.622491-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E640:EE_|DM4PR12MB5890:EE_ X-MS-Office365-Filtering-Correlation-Id: 54a912ea-65b0-4504-6084-08dad7193d6a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: h5WNjcicmMVeYE3+iM432qfkHr6pKivq3Ca1OLkIGkvW3zN2MmtrcqkPySKV/ORSnYpcvT2HRgGSFQwIZPFHm46m8uAmPle76ZTKfk1cMstA6L58nhac5+fLIGdELk9eDrj7SbgNVrN3jvXKOEDJPrS9jN1OMBX8POVeUcIp/uOKAzok3ZNSLWdTuPaIpcxktra349dNMsccVun3vCHRwrP6/I4BoW2fsYwiWOeQlNMRpi2xJe+rHzM2bjmcPAjit083hC2NVC5wDhyqy/moRN26IEbY3YN4GfYok/snID9gosYb47p/4U0iIPccSAcWepnEeQPMKjrZP17G43PgCKR64rpOUU+HFVXFRedX+gLrcuFIx8pjMuly1/BqUZxYIemOeo9KBzhY50LVus6zDqfGIErihpWu7XMgIFxGZrvktv69vfeoeb0dTKc1L34r8a8zc7khEPpCbi7cMSRySQZi9sHwpqNV4nEbHwzYqqJpDtTzYVKh24Bjcn+fBmSHo7AH6HBJikqgr3URlJ/OGH26nLu4LYQA0t/S3fHMCrXvw2ONsm6Qc1JtohXJ4sAt/CI7dew7ehlhcVqzgDoqnTsCLXy19hAj8an8g8u6phfBusDV8I4kKfvocuw09hKHNFNWaO9pfXCHjdiRZCmkl6rxJ7xsXsgRDf1eXwdhVOX50J4hznZH8zAjuQOqR9qjiVCdbfScmpdik6lEfz1EYIV8cPGVn/G16UgfFLezhMg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(136003)(346002)(376002)(451199015)(46966006)(40470700004)(36840700001)(36756003)(7416002)(81166007)(86362001)(41300700001)(40460700003)(8936002)(4326008)(2906002)(44832011)(5660300002)(82740400003)(36860700001)(83380400001)(356005)(70206006)(70586007)(478600001)(2616005)(6916009)(54906003)(316002)(40480700001)(8676002)(82310400005)(336012)(16526019)(1076003)(47076005)(426003)(6666004)(186003)(7696005)(26005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 23:34:23.0101 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54a912ea-65b0-4504-6084-08dad7193d6a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E640.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5890 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add the AMD Automatic IBRS feature bit to those being propagated to the guest, and enable the guest EFER bit. Signed-off-by: Kim Phillips --- arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/reverse_cpuid.h | 2 ++ arch/x86/kvm/svm/svm.c | 3 +++ arch/x86/kvm/x86.c | 3 +++ 4 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index dd0fe79521eb..0ed3ad3e9341 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -732,7 +732,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_init_scattered(CPUID_8000_0021_EAX, SF(NO_NESTED_DATA_BP) | SF(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | - SF(NULL_SEL_CLR_BASE) | 0 /* PrefetchCtlMsr */ + SF(NULL_SEL_CLR_BASE) | SF(AUTOIBRS) | 0 /* PrefetchCtlMsr */ ); if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index 184614e27d5b..0bf02c02bb0a 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -30,6 +30,7 @@ enum kvm_only_cpuid_leafs { #define KVM_X86_FEATURE_NO_NESTED_DATA_BP KVM_X86_FEATURE(CPUID_8000_0021_EAX, 0) #define KVM_X86_FEATURE_LFENCE_RDTSC KVM_X86_FEATURE(CPUID_8000_0021_EAX, 2) #define KVM_X86_FEATURE_NULL_SEL_CLR_BASE KVM_X86_FEATURE(CPUID_8000_0021_EAX, 6) +#define KVM_X86_FEATURE_AUTOIBRS KVM_X86_FEATURE(CPUID_8000_0021_EAX, 8) struct cpuid_reg { u32 function; @@ -89,6 +90,7 @@ static __always_inline u32 __feature_translate(int x86_feature) case X86_FEATURE_NO_NESTED_DATA_BP: return KVM_X86_FEATURE_NO_NESTED_DATA_BP; case X86_FEATURE_LFENCE_RDTSC: return KVM_X86_FEATURE_LFENCE_RDTSC; case X86_FEATURE_NULL_SEL_CLR_BASE: return KVM_X86_FEATURE_NULL_SEL_CLR_BASE; + case X86_FEATURE_AUTOIBRS: return KVM_X86_FEATURE_AUTOIBRS; default: break; } diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index ce362e88a567..1551a791cff0 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4946,6 +4946,9 @@ static __init int svm_hardware_setup(void) tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX); + if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) + kvm_enable_efer_bits(EFER_AUTOIBRS); + /* Check for pause filtering support */ if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { pause_filter_count = 0; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 2835bd796639..0697d444c715 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1688,6 +1688,9 @@ static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) { + if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS)) + return false; + if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) return false;