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Peter Anvin" , Alexey Kardashevskiy Subject: [PATCH kernel v2 3/3] x86/sev: Do not handle #VC for DR7 read/write Date: Fri, 9 Dec 2022 15:38:04 +1100 Message-ID: <20221209043804.942352-4-aik@amd.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221209043804.942352-1-aik@amd.com> References: <20221209043804.942352-1-aik@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT046:EE_|SA1PR12MB5614:EE_ X-MS-Office365-Filtering-Correlation-Id: 053b0ce6-40e1-4184-ff14-08dad99f796f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CiYYGB2mnN4NrnYa9ipzSwt799X2Geo0ftBZRfnBWH5BSoViPCOLEQJK1nHK2fzdWtZO0KHUckn9mVWjal5ixPsHuZEkAYdmpj8dZ+kdgZcSq4/KGoShz9g12YORbTFB75vB+/RHkOyd8x2hbGD5pseXoB4LQ54JfDfvt+mkb4Y9z3g/oAMUpjwxYzOOOmr7RVtS2LGs4GFNycpspxMpiIvNT5JQ/TsNF3Za0wPkvP6fOnvQMH7upcCYV+uqjHOFJaXujN+rtmRGY7UPdHJXAUB1gTg2GXb8/WxX6ty47Hd7wmpVzupj+4+GRnZ5id5wkLYhpNxwhyYdM+f580q3LnR7K1e2mjT19fHX0Vvi45RDkqLx7Aed/nq4hn9oxH7HA4lg4PkxdGHJYm4dQb02e6y/33l0Kv6Md+u7OUE6uSh5V1p5PUSOSnihsy0b/Ral9h9PT6UeI6IM0AgVKzDlRZLqPf6QkF0ttxy88I66FTJKSUrTSQPHlc6KjSeKULdBSW/wOJ0T1epP10xsqF3lSdRyifz513USC+dnxI5Yc1S5wBTPxchphRudezuPRR9Q8x3ZShBG6te6FPTLbi7boSiuc8WmRUDpKpVqeKr0BGZC0h46CUH/m2DJxCm/i9MA4prBjEDM6yCFHKuUDaClQuzwE7BTR2ZpgjJWd/1xgVttdvETDNOVzNNcjikiWHNIIt5tx3QSCVxINorVbB29tsjtk7uvVdwdvSfksDxq0WI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(396003)(346002)(39860400002)(376002)(451199015)(40470700004)(36840700001)(46966006)(6916009)(426003)(81166007)(54906003)(356005)(316002)(4326008)(336012)(40480700001)(47076005)(36860700001)(26005)(2616005)(16526019)(1076003)(70586007)(6666004)(70206006)(186003)(36756003)(478600001)(82310400005)(8676002)(82740400003)(41300700001)(7416002)(5660300002)(8936002)(40460700003)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2022 04:40:04.5048 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 053b0ce6-40e1-4184-ff14-08dad99f796f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5614 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org With MSR_AMD64_SEV_DEBUG_SWAP enabled, the VM should not get #VC events for DR7 read/write which it rather avoided. Signed-off-by: Alexey Kardashevskiy Reviewed-by: Borislav Petkov (AMD) --- Changes: v2: * use new bit definition --- arch/x86/include/asm/msr-index.h | 1 + tools/arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/sev.c | 6 ++++++ 3 files changed, 8 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 4a2af82553e4..979ea2dd3845 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -570,6 +570,7 @@ #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) +#define MSR_AMD64_SEV_DEBUG_SWAP BIT_ULL(7) #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index f17ade084720..2264ada2e26a 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -570,6 +570,7 @@ #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) +#define MSR_AMD64_SEV_DEBUG_SWAP BIT_ULL(7) #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index a428c62330d3..6141c789e3d5 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1618,6 +1618,9 @@ static enum es_result vc_handle_dr7_write(struct ghcb *ghcb, long val, *reg = vc_insn_get_rm(ctxt); enum es_result ret; + if (sev_status & MSR_AMD64_SEV_DEBUG_SWAP) + return ES_VMM_ERROR; + if (!reg) return ES_DECODE_FAILED; @@ -1655,6 +1658,9 @@ static enum es_result vc_handle_dr7_read(struct ghcb *ghcb, struct sev_es_runtime_data *data = this_cpu_read(runtime_data); long *reg = vc_insn_get_rm(ctxt); + if (sev_status & MSR_AMD64_SEV_DEBUG_SWAP) + return ES_VMM_ERROR; + if (!reg) return ES_DECODE_FAILED;