From patchwork Tue Dec 20 06:36:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 13077547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D15A6C4332F for ; Tue, 20 Dec 2022 07:02:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233545AbiLTHCw (ORCPT ); Tue, 20 Dec 2022 02:02:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232887AbiLTHBo (ORCPT ); Tue, 20 Dec 2022 02:01:44 -0500 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0B8F15FDF; Mon, 19 Dec 2022 23:01:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671519700; x=1703055700; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cFa67ljZDOj6B4hnKmSyOvFw/+uBlbUZju1/l5Toj94=; b=bssOtzC1EihsWMNGwXyi8KsQIb6P94dulS/RQW2o/Hu3Ei3wZpXo3uUz BR3lzhuL3u+3YdCULK/GcQ6GGLxGGGq+hOD4aKzABEas9Nd5YUZE3kztV XUo5TScwIQ8Wlrzmtg1mSNzgS07safNFvOZ7lAaPnVYryvS9FmZq/lMfF 9XfUbSVJUloTIJ14MlBRAGTny/4c5zSkk4JEYRYFM5zinB4tUN9AegAKz yUg2mgnWZZ/6xfo7Qwc4pLw8ipQ/LJ8wIVjmVi3WFCA4saaPVlVSdXSmq d3mI/2TE4XyDKjh5PqsZprm+Ws4wSjhNCLfIWqaBwB+KRGLvaGDq1XZG4 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="302972128" X-IronPort-AV: E=Sophos;i="5.96,258,1665471600"; d="scan'208";a="302972128" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2022 23:01:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="644326530" X-IronPort-AV: E=Sophos;i="5.96,258,1665471600"; d="scan'208";a="644326530" Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga007.jf.intel.com with ESMTP; 19 Dec 2022 23:01:17 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [RFC PATCH 25/32] x86/fred: disallow the swapgs instruction when FRED is enabled Date: Mon, 19 Dec 2022 22:36:51 -0800 Message-Id: <20221220063658.19271-26-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221220063658.19271-1-xin3.li@intel.com> References: <20221220063658.19271-1-xin3.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: "H. Peter Anvin (Intel)" The FRED architecture establishes the full supervisor/user through: 1) FRED event delivery swaps the value of the GS base address and that of the IA32_KERNEL_GS_BASE MSR. 2) ERETU swaps the value of the GS base address and that of the IA32_KERNEL_GS_BASE MSR. Thus, the swapgs instruction is disallowed when FRED is enabled, otherwise it cauess #UD. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/kernel/process_64.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index bfe6179b7a17..5b6cfd2ca630 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -165,7 +165,8 @@ static noinstr unsigned long __rdgsbase_inactive(void) lockdep_assert_irqs_disabled(); - if (!static_cpu_has(X86_FEATURE_XENPV)) { + if (!cpu_feature_enabled(X86_FEATURE_FRED) && + !static_cpu_has(X86_FEATURE_XENPV)) { native_swapgs(); gsbase = rdgsbase(); native_swapgs(); @@ -190,7 +191,8 @@ static noinstr void __wrgsbase_inactive(unsigned long gsbase) { lockdep_assert_irqs_disabled(); - if (!static_cpu_has(X86_FEATURE_XENPV)) { + if (!cpu_feature_enabled(X86_FEATURE_FRED) && + !static_cpu_has(X86_FEATURE_XENPV)) { native_swapgs(); wrgsbase(gsbase); native_swapgs();