| Message ID | 20221230035928.3423990-3-reijiw@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: arm64: PMU: Allow userspace to limit the number of PMCs on vCPU | expand |
On Thu, Dec 29, 2022 at 07:59:23PM -0800, Reiji Watanabe wrote: > The default reset function for PMU registers (reset_pmu_reg()) > now simply clears a specified register. Use that function for > PMUSERENR_EL0 and PMCCFILTR_EL0, since those registers should > simply be cleared on vCPU reset. AFAICT, the fields in both these registers have UNKNOWN reset values. Of course, 0 is an entirely valid reset value but the architectural behavior should be mentioned in the commit message. -- Thanks, Oliver
Hi Oliver, On Sun, Jan 8, 2023 at 11:13 AM Oliver Upton <oliver.upton@linux.dev> wrote: > > On Thu, Dec 29, 2022 at 07:59:23PM -0800, Reiji Watanabe wrote: > > The default reset function for PMU registers (reset_pmu_reg()) > > now simply clears a specified register. Use that function for > > PMUSERENR_EL0 and PMCCFILTR_EL0, since those registers should > > simply be cleared on vCPU reset. > > AFAICT, the fields in both these registers have UNKNOWN reset values. Of > course, 0 is an entirely valid reset value but the architectural > behavior should be mentioned in the commit message. Uh, yeah, the commit message was misleading. The fields in both these registers have UNKNOWN reset values. The ones for 32bit registers (PMUSERENR and PMCCFILTR) have zero reset values though. I will update the commit message to mention those explicitly. Thank you, Reiji
On Mon, Jan 09, 2023 at 05:17:59PM -0800, Reiji Watanabe wrote: > On Sun, Jan 8, 2023 at 11:13 AM Oliver Upton <oliver.upton@linux.dev> wrote: > > > > On Thu, Dec 29, 2022 at 07:59:23PM -0800, Reiji Watanabe wrote: > > > The default reset function for PMU registers (reset_pmu_reg()) > > > now simply clears a specified register. Use that function for > > > PMUSERENR_EL0 and PMCCFILTR_EL0, since those registers should > > > simply be cleared on vCPU reset. > > > > AFAICT, the fields in both these registers have UNKNOWN reset values. Of > > course, 0 is an entirely valid reset value but the architectural > > behavior should be mentioned in the commit message. > > Uh, yeah, the commit message was misleading. > The fields in both these registers have UNKNOWN reset values. > The ones for 32bit registers (PMUSERENR and PMCCFILTR) have zero reset > values though. Gosh, that silly (but highly relevant) detail escaped me. > I will update the commit message to mention those explicitly. Thanks! -- Best, Oliver
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index ec4bdaf71a15..4959658b502c 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1747,7 +1747,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { * in 32bit mode. Here we choose to reset it as zero for consistency. */ { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr, - .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, + .reg = PMUSERENR_EL0 }, { PMU_SYS_REG(SYS_PMOVSSET_EL0), .access = access_pmovs, .reg = PMOVSSET_EL0 }, @@ -1903,7 +1903,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { * in 32bit mode. Here we choose to reset it as zero for consistency. */ { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper, - .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, + .reg = PMCCFILTR_EL0 }, { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
The default reset function for PMU registers (reset_pmu_reg()) now simply clears a specified register. Use that function for PMUSERENR_EL0 and PMCCFILTR_EL0, since those registers should simply be cleared on vCPU reset. No functional change intended. Signed-off-by: Reiji Watanabe <reijiw@google.com> --- arch/arm64/kvm/sys_regs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)