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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , "Konrad Rzeszutek Wilk" , Paolo Bonzini , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , Alexey Kardashevskiy , , , Subject: [PATCH v6 3/7] x86/cpu, kvm: Move the LFENCE_RDTSC / LFENCE always serializing feature Date: Tue, 10 Jan 2023 16:46:39 -0600 Message-ID: <20230110224643.452273-5-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230110224643.452273-1-kim.phillips@amd.com> References: <20230110224643.452273-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00001A61:EE_|MN0PR12MB6056:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d344ebc-8874-40a8-a839-08daf35cae60 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eIdNa3GBBN0sWmBeW1jmq+XRL2n4jVJWNl0ufBYFdaW/LiwSaZIsrWn6bycXoGFXelmTbvNiq/UVLvdLiSadLtTQJy+0+v28sv89Dxa8hfTVTGmTVF4sIXyVGOssH9Fhyzhgvdigtsg98PTHzqmrkdpLSTmexDvsLFImTm/xWwOIIc+F2ZYhxE15ZsueS1dkVIuzDyU5rbqfiWjWZNiIoVYXXVvHQQsn7qfJfJLqHWBgtSA5RYhdcagCs1QSb/+s2NYW3s+MfYyrqiVogfdzGCkeaa1GTlXHSIBeJHXIJ7iSnYtOO0sYKehkRnvujMZP+g1216ktdoG2gxVFgYBwuLzw1jJsFND50hxf8n/Q5Cx8dj0HuI1pAeWm+QXLk9l1qv/MDN3V07Q4wYbcoNLnYjp8tpG60YnzpNMumVSgbQu/Dzn54akJNe0bjGfBP9jcmAtKRjY8K1HvOvXNlwC0GZOLrZELRxwu0rkscS69s0GE3DjTmLnyOyMuLjweiRYsd/EZ+Jc87y5lm1+pEFZo8hE0YUZb1zdjiTomFHPlkcHHcbkomBlaACzVJNmkgsiiH1tTC1ZVMKChJE0EiPJxzgryUIUX7XuWi0RgWpByMnz37TuwmH2JC0wLs1YcbgvpTRGtlLNDCnTaF50zilYmfl8QYmC1zMXCqnGfXnItqOlz3Ymvmq6IDTC84S/j5inKuTtcyiNjQrYj9r5kST/TFGspSZDmST3tmdhzMfSiiNs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(39860400002)(376002)(396003)(136003)(451199015)(40470700004)(46966006)(36840700001)(7416002)(44832011)(2906002)(36860700001)(426003)(41300700001)(5660300002)(7696005)(356005)(36756003)(8936002)(8676002)(70586007)(70206006)(4326008)(63370400001)(83380400001)(63350400001)(40460700003)(6916009)(86362001)(54906003)(47076005)(336012)(82310400005)(1076003)(2616005)(26005)(478600001)(81166007)(186003)(16526019)(316002)(40480700001)(82740400003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jan 2023 22:47:41.2894 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d344ebc-8874-40a8-a839-08daf35cae60 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00001A61.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6056 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The LFENCE_RDTSC / LFENCE always serializing feature was a scattered bit and open-coded for KVM in __do_cpuid_func(). Add it to its newly added CPUID leaf 0x80000021 EAX proper, and propagate it in kvm_set_cpu_caps() instead. Also drop the bit description comments now it's more self-describing. Whilst there, switch to using the more efficient cpu_feature_enabled() instead of static_cpu_has(). Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeatures.h | 3 ++- arch/x86/kvm/cpuid.c | 9 ++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 0cd7b4afd528..79da8e492c0f 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -97,7 +97,7 @@ #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */ -#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ +/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */ #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ @@ -428,6 +428,7 @@ /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" AMD No Nested Data Breakpoints */ +#define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ /* * BUG word(s) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 69e433e4e9ff..88c970046c10 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -742,8 +742,10 @@ void kvm_set_cpu_caps(void) F(SME_COHERENT)); kvm_cpu_cap_mask(CPUID_8000_0021_EAX, - F(NO_NESTED_DATA_BP) + F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) ); + if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) + kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); kvm_cpu_cap_mask(CPUID_C000_0001_EDX, F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | @@ -1229,7 +1231,6 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) cpuid_entry_override(entry, CPUID_8000_0021_EAX); /* * Pass down these bits: - * EAX 2 LAS, LFENCE always serializing * EAX 6 NSCB, Null selector clear base * * Other defined bits are for MSRs that KVM does not expose: @@ -1239,10 +1240,8 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) * KVM doesn't support SMM_CTL. * EAX 9 SMM_CTL MSR is not supported */ - entry->eax &= BIT(2) | BIT(6); + entry->eax &= BIT(6); entry->eax |= BIT(9); - if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)) - entry->eax |= BIT(2); if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) entry->eax |= BIT(6); break;