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Fri, 27 Jan 2023 11:42:07 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Fri, 27 Jan 2023 11:42:06 +0000 Received: from e124191.cambridge.arm.com (10.1.197.45) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Fri, 27 Jan 2023 11:42:01 +0000 From: Joey Gouly To: Andrew Jones , , CC: , Alexandru Elisei , Christoffer Dall , Fuad Tabba , Jean-Philippe Brucker , Joey Gouly , Marc Zyngier , Mark Rutland , Oliver Upton , Paolo Bonzini , Quentin Perret , Steven Price , Suzuki K Poulose , "Thomas Huth" , Will Deacon , Zenghui Yu , , , , Subject: [RFC kvm-unit-tests 09/27] arm: realm: Add support for changing the state of memory Date: Fri, 27 Jan 2023 11:40:50 +0000 Message-ID: <20230127114108.10025-10-joey.gouly@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230127114108.10025-1-joey.gouly@arm.com> References: <20230127112248.136810-1-suzuki.poulose@arm.com> <20230127114108.10025-1-joey.gouly@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT048:EE_|DU0PR08MB9079:EE_|DBAEUR03FT025:EE_|AS8PR08MB7919:EE_ X-MS-Office365-Filtering-Correlation-Id: e7782b56-79fd-4bf4-7487-08db005b8ca4 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2023 11:42:20.4512 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7782b56-79fd-4bf4-7487-08db005b8ca4 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT025.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB7919 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org For a Realm, the guest physical address (in reality the IPA/GPA of the VM) has an associated state (Realm IPA State, RIPAS) which is either of : RIPAS_RAM RIPAS_EMPTY The state of the physical address decides certain behaviors. e.g., any access to a RIPAS_EMPTY PA will generate a Synchronous External Abort back to the Realm, from the RMM. All "PA" that represents RAM for the Realm, must be set to RIPAS_RAM before an access is made. When the initial image (e.g., test, DTB) of a Realm is loaded, the hypervisor/VMM can transition the state of the loaded "area" to RIPAS_RAM. The rest of the "RAM" must be transitioned by the test payload before any access is made. Similarly, a Realm could set an "IPA" to RIPAS_EMPTY, when it is about to use the "unprotected" alias of the IPA. This is a hint for the host to reclaim the page from the protected "IPA. This patchs adds supporting helpers for setting the IPA state from Realm. These will be used later for the Realm. Co-developed-by: Suzuki K Poulose Signed-off-by: Suzuki K Poulose Signed-off-by: Joey Gouly --- lib/arm/mmu.c | 1 + lib/arm64/asm/rsi.h | 8 ++++++++ lib/arm64/rsi.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 53 insertions(+) diff --git a/lib/arm/mmu.c b/lib/arm/mmu.c index 6f1f42f5..2b5a7141 100644 --- a/lib/arm/mmu.c +++ b/lib/arm/mmu.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "alloc_page.h" #include "vmalloc.h" diff --git a/lib/arm64/asm/rsi.h b/lib/arm64/asm/rsi.h index 8b9b91b2..c8179341 100644 --- a/lib/arm64/asm/rsi.h +++ b/lib/arm64/asm/rsi.h @@ -33,4 +33,12 @@ static inline bool is_realm(void) return rsi_present; } +enum ripas_t { + RIPAS_EMPTY, + RIPAS_RAM, +}; + +void arm_set_memory_protected(unsigned long va, size_t size); +void arm_set_memory_shared(unsigned long va, size_t size); + #endif /* __ASMARM64_RSI_H_ */ diff --git a/lib/arm64/rsi.c b/lib/arm64/rsi.c index 23a4e963..08c77889 100644 --- a/lib/arm64/rsi.c +++ b/lib/arm64/rsi.c @@ -65,3 +65,47 @@ void arm_rsi_init(void) /* Set the upper bit of the IPA as the NS_SHARED pte attribute */ prot_ns_shared = (1UL << phys_mask_shift); } + +static unsigned rsi_set_addr_range_state(unsigned long start, unsigned long size, + enum ripas_t state, unsigned long *top) +{ + struct smccc_result res; + + rsi_invoke(SMC_RSI_IPA_STATE_SET, start, size, state, 0, 0, 0, 0, 0, 0, 0, 0, &res); + *top = res.r1; + return res.r0; +} + +static void arm_set_memory_state(unsigned long start, + unsigned long size, + unsigned int ripas) +{ + int ret; + unsigned long end, top; + unsigned long old_start = start; + + if (!is_realm()) + return; + + start = ALIGN_DOWN(start, RSI_GRANULE_SIZE); + if (start != old_start) + size += old_start - start; + end = ALIGN(start + size, RSI_GRANULE_SIZE); + while (start != end) { + ret = rsi_set_addr_range_state(start, (end - start), + ripas, &top); + assert(!ret); + assert(top <= end); + start = top; + } +} + +void arm_set_memory_protected(unsigned long start, unsigned long size) +{ + arm_set_memory_state(start, size, RIPAS_RAM); +} + +void arm_set_memory_shared(unsigned long start, unsigned long size) +{ + arm_set_memory_state(start, size, RIPAS_EMPTY); +}