| Message ID | 20230127182558.2416400-4-atishp@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM perf support | expand |
Yo Atish, On Fri, Jan 27, 2023 at 10:25:47AM -0800, Atish Patra wrote: > This patch fixes/improve few minor things in SBI PMU extension > definition. > > 1. Align all the firmware event names. > @@ -171,7 +171,7 @@ enum sbi_pmu_fw_generic_events_t { > SBI_PMU_FW_IPI_RECVD = 7, > - SBI_PMU_FW_FENCE_I_RECVD = 9, > + SBI_PMU_FW_FENCE_I_RCVD = 9, > SBI_PMU_FW_SFENCE_VMA_RCVD = 11, Alignment looks incomplete to me! Looks like you went from 2 RECVD and 1 RCVD to 2 RCVD and 1 RECVD! FWIW, the spec uses RECEIVED for all of these: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc#114-event-firmware-events-type-15 Thanks, Conor.
On Fri, Jan 27, 2023 at 2:53 PM Conor Dooley <conor@kernel.org> wrote: > > Yo Atish, > > On Fri, Jan 27, 2023 at 10:25:47AM -0800, Atish Patra wrote: > > This patch fixes/improve few minor things in SBI PMU extension > > definition. > > > > 1. Align all the firmware event names. > > > @@ -171,7 +171,7 @@ enum sbi_pmu_fw_generic_events_t { > > SBI_PMU_FW_IPI_RECVD = 7, > > - SBI_PMU_FW_FENCE_I_RECVD = 9, > > + SBI_PMU_FW_FENCE_I_RCVD = 9, > > SBI_PMU_FW_SFENCE_VMA_RCVD = 11, > > Alignment looks incomplete to me! Looks like you went from 2 RECVD and > 1 RCVD to 2 RCVD and 1 RECVD! FWIW, the spec uses RECEIVED for all of Ahh I missed the other one. I have changed everything to RCVD just to keep it short. "RECEIVED" is too long :) > these: > https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc#114-event-firmware-events-type-15 > > Thanks, > Conor. >
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 4ca7fba..f21c026 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -171,7 +171,7 @@ enum sbi_pmu_fw_generic_events_t { SBI_PMU_FW_IPI_SENT = 6, SBI_PMU_FW_IPI_RECVD = 7, SBI_PMU_FW_FENCE_I_SENT = 8, - SBI_PMU_FW_FENCE_I_RECVD = 9, + SBI_PMU_FW_FENCE_I_RCVD = 9, SBI_PMU_FW_SFENCE_VMA_SENT = 10, SBI_PMU_FW_SFENCE_VMA_RCVD = 11, SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12, @@ -215,6 +215,9 @@ enum sbi_pmu_ctr_type { #define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06 #define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01 +#define SBI_PMU_EVENT_CACHE_ID_SHIFT 3 +#define SBI_PMU_EVENT_CACHE_OP_SHIFT 1 + #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF /* Flags defined for config matching function */
This patch fixes/improve few minor things in SBI PMU extension definition. 1. Align all the firmware event names. 2. Add macros for bit positions in cache event ID & ops. The changes were small enough to combine them together instead of creating 1 liner patches. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/sbi.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)