From patchwork Sun Feb 5 01:15:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13128915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AB1FC63797 for ; Sun, 5 Feb 2023 01:15:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230175AbjBEBP2 (ORCPT ); Sat, 4 Feb 2023 20:15:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229995AbjBEBP0 (ORCPT ); Sat, 4 Feb 2023 20:15:26 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FC6725968 for ; Sat, 4 Feb 2023 17:15:24 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id m13so8858704plx.13 for ; Sat, 04 Feb 2023 17:15:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=svX9QoI7+pu9KPeMOFBJn1yDl6Mnh/aSAvVAOGuYZfA=; b=UWWqvu8ePBkTP/f/Im+K0H/bNL/4zKa4o1kI6YLXeiV/XRHxhnq/UqlTohNKQYSFfd m2UxfODelUBj4tsTSem8Ta5Um6OpE9jup1MJsc1vyMgbmWEMWodnGydA9Npw8rqoB3Nr zyQQzmAj10eUlrfRefLVvB8HXB+CVmvso7lp1k8XGnFcDQxrESBPR5vMhiUPN7et66eC E0/TWd/Qbctc9NzaDESSuyCAIrC3vglE0+oE9UrDJ+wJi52VhxA/FwMQhCFh/a+LEHM/ E+BC8uoYtypHLFQaNyX12aSHnxo1s5C9lt8NjtST+gBDTrBDiT59LguPB7YhM4WPOHAl rauQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=svX9QoI7+pu9KPeMOFBJn1yDl6Mnh/aSAvVAOGuYZfA=; b=M6eatvGxrYc8rjCttBwN8D+rXSrZRg85CZYwAOr1PebkNmRfWrZMySV147gw3lKAHK uW4L7KunUM/iIPT+sefRhoocLI7AhfG2hCV/2fe3eBjKuREBun5pIKQgISIIMTy/Ms4e uV4SjFiNaPXpVaLXQLCjSc7Vqm+dXEFzSUm91TUl/d6Wp9KHYNPkNAaA2mbZ2ZNKpMai dJsCKsXheDBrl+N0/2A3ao7f5I9+vNt1/Tq3BXdHykHeEwsUoC/JKkAUjDRr0oQHgSYm GSsdY2IUXHnJvq8FojM/vyYzGy/awoK1PjI1W60Qzl4rOG+26tA0zjF5ZdWB94n+E6W0 PoCg== X-Gm-Message-State: AO0yUKWzbLmZYESwNwjCdPJL/AKjnGfJisBlhtoCuwywSPFqG7u3LXz7 qkWWsob7sjMkJdWwFtGlDh360xAsC9OrMrO0 X-Google-Smtp-Source: AK7set+Xyt5S9nTOhNQhOx6D8ZIswnKXzhNJjKsuo14bbUAnnbqzHvHmwnIDP5qP1M47Lk99is8gOw== X-Received: by 2002:a17:90b:4a4c:b0:226:c196:db55 with SMTP id lb12-20020a17090b4a4c00b00226c196db55mr16098855pjb.18.1675559723756; Sat, 04 Feb 2023 17:15:23 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id c7-20020a17090a020700b0023080c4c3bcsm2721917pjc.31.2023.02.04.17.15.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Feb 2023 17:15:23 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Andrew Jones , Albert Ou , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Will Deacon Subject: [PATCH v5 01/14] perf: RISC-V: Define helper functions expose hpm counter width and count Date: Sat, 4 Feb 2023 17:15:02 -0800 Message-Id: <20230205011515.1284674-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230205011515.1284674-1-atishp@rivosinc.com> References: <20230205011515.1284674-1-atishp@rivosinc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org KVM module needs to know how many hardware counters and the counter width that the platform supports. Otherwise, it will not be able to show optimal value of virtual counters to the guest. The virtual hardware counters also need to have the same width as the logical hardware counters for simplicity. However, there shouldn't be mapping between virtual hardware counters and logical hardware counters. As we don't support hetergeneous harts or counters with different width as of now, the implementation relies on the counter width of the first available programmable counter. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 37 ++++++++++++++++++++++++++++++++-- include/linux/perf/riscv_pmu.h | 3 +++ 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index f6507ef..6b53adc 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -44,7 +44,7 @@ static const struct attribute_group *riscv_pmu_attr_groups[] = { }; /* - * RISC-V doesn't have hetergenous harts yet. This need to be part of + * RISC-V doesn't have heterogeneous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters */ static union sbi_pmu_ctr_info *pmu_ctr_list; @@ -52,6 +52,9 @@ static bool riscv_pmu_use_irq; static unsigned int riscv_pmu_irq_num; static unsigned int riscv_pmu_irq; +/* Cache the available counters in a bitmask */ +static unsigned long cmask; + struct sbi_pmu_event_data { union { union { @@ -267,6 +270,37 @@ static bool pmu_sbi_ctr_is_fw(int cidx) return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false; } +/* + * Returns the counter width of a programmable counter and number of hardware + * counters. As we don't support heterogeneous CPUs yet, it is okay to just + * return the counter width of the first programmable counter. + */ +int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr) +{ + int i; + union sbi_pmu_ctr_info *info; + u32 hpm_width = 0, hpm_count = 0; + + if (!cmask) + return -EINVAL; + + for_each_set_bit(i, &cmask, RISCV_MAX_COUNTERS) { + info = &pmu_ctr_list[i]; + if (!info) + continue; + if (!hpm_width && info->csr != CSR_CYCLE && info->csr != CSR_INSTRET) + hpm_width = info->width; + if (info->type == SBI_PMU_CTR_TYPE_HW) + hpm_count++; + } + + *hw_ctr_width = hpm_width; + *num_hw_ctr = hpm_count; + + return 0; +} +EXPORT_SYMBOL_GPL(riscv_pmu_get_hpm_info); + static int pmu_sbi_ctr_get_idx(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; @@ -812,7 +846,6 @@ static void riscv_pmu_destroy(struct riscv_pmu *pmu) static int pmu_sbi_device_probe(struct platform_device *pdev) { struct riscv_pmu *pmu = NULL; - unsigned long cmask = 0; int ret = -ENODEV; int num_counters; diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index e17e86a..a1c3f77 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -73,6 +73,9 @@ void riscv_pmu_legacy_skip_init(void); static inline void riscv_pmu_legacy_skip_init(void) {}; #endif struct riscv_pmu *riscv_pmu_alloc(void); +#ifdef CONFIG_RISCV_PMU_SBI +int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr); +#endif #endif /* CONFIG_RISCV_PMU */