| Message ID | 20230221163655.920289-8-mizhang@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Overhauling amx_test | expand |
On Tue, Feb 21, 2023, Mingwei Zhang wrote: > Fix the checks to XFD_ERR using logical AND operation because XFD_ERR might > contain more information in the future. According Intel SDM Vol 1. 13.14: If that happens, then the future change is responsible for updating the check. The test very clearly does a straight write of MSR_IA32_XFD. If there are extra bits set then something is broken. wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILEDATA);
diff --git a/tools/testing/selftests/kvm/x86_64/amx_test.c b/tools/testing/selftests/kvm/x86_64/amx_test.c index 296c954dfd6d..62fff3363b3b 100644 --- a/tools/testing/selftests/kvm/x86_64/amx_test.c +++ b/tools/testing/selftests/kvm/x86_64/amx_test.c @@ -217,10 +217,10 @@ void guest_nm_handler(struct ex_regs *regs) /* Check if #NM is triggered by XFEATURE_MASK_XTILEDATA */ GUEST_SYNC(7); GUEST_ASSERT((get_cr0() & X86_CR0_TS) == 0); - GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA); + GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) & XFEATURE_MASK_XTILEDATA); GUEST_ASSERT(rdmsr(MSR_IA32_XFD) & XFEATURE_MASK_XTILEDATA); GUEST_SYNC(8); - GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA); + GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) & XFEATURE_MASK_XTILEDATA); GUEST_ASSERT(rdmsr(MSR_IA32_XFD) & XFEATURE_MASK_XTILEDATA); /* Clear xfd_err */ wrmsr(MSR_IA32_XFD_ERR, 0);
Fix the checks to XFD_ERR using logical AND operation because XFD_ERR might contain more information in the future. According Intel SDM Vol 1. 13.14: "Specifically, the MSR is loaded with the logical AND of the IA32_XFD MSR and the bitmap corresponding to the state component(s) required by the faulting instruction." So fix the check by using AND instead of '=='. Signed-off-by: Mingwei Zhang <mizhang@google.com> --- tools/testing/selftests/kvm/x86_64/amx_test.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)