diff mbox series

[v1,3/3] KVM: arm64: Enable writable for all fields in ID_DFR0_EL1

Message ID 20230326011950.405749-4-jingzhangos@google.com (mailing list archive)
State New, archived
Headers show
Series Enable writable for ID_AA64DFR0_EL1 and ID_DFR0_EL1 | expand

Commit Message

Jing Zhang March 26, 2023, 1:19 a.m. UTC 
All valid fields in ID_DFR0_EL1 are writable from usrespace with this
change.

Signed-off-by: Jing Zhang <jingzhangos@google.com>
---
 arch/arm64/kvm/id_regs.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
index e64152aa448b..7dc2fb8121f3 100644
--- a/arch/arm64/kvm/id_regs.c
+++ b/arch/arm64/kvm/id_regs.c
@@ -565,8 +565,22 @@  static struct id_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
 		.set_user = set_id_dfr0_el1,
 		.visibility = aa32_id_visibility, },
 	  .ftr_bits = {
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_DFR0_EL1_CopDbg_SHIFT, ID_DFR0_EL1_CopDbg_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_DFR0_EL1_CopSDbg_SHIFT, ID_DFR0_EL1_CopSDbg_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_DFR0_EL1_MMapDbg_SHIFT, ID_DFR0_EL1_MMapDbg_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_DFR0_EL1_CopTrc_SHIFT, ID_DFR0_EL1_CopTrc_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_DFR0_EL1_MMapTrc_SHIFT, ID_DFR0_EL1_MMapTrc_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_DFR0_EL1_MProfDbg_SHIFT, ID_DFR0_EL1_MProfDbg_WIDTH, 0),
 		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
 			ID_DFR0_EL1_PerfMon_SHIFT, ID_DFR0_EL1_PerfMon_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_DFR0_EL1_TraceFilt_SHIFT, ID_DFR0_EL1_TraceFilt_WIDTH, 0),
 		ARM64_FTR_END, },
 	  .init = init_id_dfr0_el1,
 	},