@@ -355,10 +355,15 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd,
u64 val)
{
- u8 pmuver, host_pmuver;
+ u8 pmuver, host_pmuver, brps, ctx_cmps;
bool valid_pmu;
int ret;
+ brps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_BRPs), val);
+ ctx_cmps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_CTX_CMPs), val);
+ if (ctx_cmps > brps)
+ return -EINVAL;
+
host_pmuver = kvm_arm_pmu_get_pmuver_limit();
/*
@@ -377,28 +382,28 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
return -EINVAL;
- if (valid_pmu) {
- mutex_lock(&vcpu->kvm->arch.config_lock);
- ret = set_id_reg(vcpu, rd, val);
- if (ret) {
- mutex_unlock(&vcpu->kvm->arch.config_lock);
- return ret;
- }
+ if (!valid_pmu) {
+ /* Igore the pmuver field in val */
+ pmuver = FIELD_GET(ID_AA64DFR0_EL1_PMUVer_MASK, read_id_reg(vcpu, rd));
+ val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
+ val |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK, pmuver);
+ }
- IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
- IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |=
- FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), pmuver_to_perfmon(pmuver));
+ mutex_lock(&vcpu->kvm->arch.config_lock);
+ ret = set_id_reg(vcpu, rd, val);
+ if (ret) {
mutex_unlock(&vcpu->kvm->arch.config_lock);
- } else {
- /* We can only differ with PMUver, and anything else is an error */
- val ^= read_id_reg(vcpu, rd);
- val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
- if (val)
- return -EINVAL;
+ return ret;
+ }
+ IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
+ IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |=
+ FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), pmuver_to_perfmon(pmuver));
+
+ if (!valid_pmu)
assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags,
pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
- }
+ mutex_unlock(&vcpu->kvm->arch.config_lock);
return 0;
}
@@ -610,7 +615,7 @@ static struct id_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
.get_user = get_id_reg,
.set_user = set_id_aa64dfr0_el1, },
.ftr_bits = ftr_id_aa64dfr0,
- .writable_mask = ID_AA64DFR0_EL1_PMUVer_MASK,
+ .writable_mask = GENMASK(63, 0),
.read_kvm_sanitised_reg = read_sanitised_id_aa64dfr0_el1,
},
ID_SANITISED(ID_AA64DFR1_EL1),
Since number of context-aware breakpoints must be no more than number of supported breakpoints according to Arm ARM, return an error if userspace tries to set CTX_CMPS field to such value. Signed-off-by: Jing Zhang <jingzhangos@google.com> --- arch/arm64/kvm/id_regs.c | 43 ++++++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 19 deletions(-)