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Peter Anvin" , Andi Kleen , Andrew Cooper , Andy Lutomirski , Asit Mallick , Cfir Cohen , Dan Williams , Dave Hansen , David Kaplan , David Rientjes , Dirk Hohndel , Erdem Aktas , Jan Kiszka , Jiri Slaby , Joerg Roedel , Juergen Gross , Kees Cook , Kirill Shutemov , Kuppuswamy Sathyanarayanan , Linus Torvalds , Mike Stunes , Peter Zijlstra , Raj Ashok , Sean Christopherson , Thomas Gleixner , Tom Lendacky , Tony Luck , kvm@vger.kernel.org, linux-coco@lists.linux.dev, x86@kernel.org, Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Jonathan Corbet , linux-doc@vger.kernel.org Subject: [RFC PATCH 2/7] x86/entry: Add IST main stack Date: Mon, 3 Apr 2023 22:06:00 +0800 Message-Id: <20230403140605.540512-3-jiangshanlai@gmail.com> X-Mailer: git-send-email 2.19.1.6.gb485710b In-Reply-To: <20230403140605.540512-1-jiangshanlai@gmail.com> References: <20230403140605.540512-1-jiangshanlai@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Lai Jiangshan Add IST main stack for atomic-IST-entry. The size is THREAD_SIZE since there might be multiple super exceptions being handled on the stack. Signed-off-by: Lai Jiangshan --- Documentation/x86/kernel-stacks.rst | 2 ++ arch/x86/include/asm/cpu_entry_area.h | 5 +++++ arch/x86/kernel/dumpstack_64.c | 6 ++++-- arch/x86/mm/cpu_entry_area.c | 1 + 4 files changed, 12 insertions(+), 2 deletions(-) diff --git a/Documentation/x86/kernel-stacks.rst b/Documentation/x86/kernel-stacks.rst index 6b0bcf027ff1..be89acf302da 100644 --- a/Documentation/x86/kernel-stacks.rst +++ b/Documentation/x86/kernel-stacks.rst @@ -105,6 +105,8 @@ The currently assigned IST stacks are: middle of switching stacks. Using IST for MCE events avoids making assumptions about the previous state of the kernel stack. +* ESTACK_IST. bla bla + For more details see the Intel IA32 or AMD AMD64 architecture manuals. diff --git a/arch/x86/include/asm/cpu_entry_area.h b/arch/x86/include/asm/cpu_entry_area.h index 462fc34f1317..a373e8c37e25 100644 --- a/arch/x86/include/asm/cpu_entry_area.h +++ b/arch/x86/include/asm/cpu_entry_area.h @@ -10,6 +10,8 @@ #ifdef CONFIG_X86_64 +#define IST_MAIN_STKSZ THREAD_SIZE + #ifdef CONFIG_AMD_MEM_ENCRYPT #define VC_EXCEPTION_STKSZ EXCEPTION_STKSZ #else @@ -30,6 +32,8 @@ char VC_stack[optional_stack_size]; \ char VC2_stack_guard[guardsize]; \ char VC2_stack[optional_stack_size]; \ + char IST_stack_guard[guardsize]; \ + char IST_stack[IST_MAIN_STKSZ]; \ char IST_top_guard[guardsize]; \ /* The exception stacks' physical storage. No guard pages required */ @@ -52,6 +56,7 @@ enum exception_stack_ordering { ESTACK_MCE, ESTACK_VC, ESTACK_VC2, + ESTACK_IST, N_EXCEPTION_STACKS }; diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c index f05339fee778..3413b23fa9f1 100644 --- a/arch/x86/kernel/dumpstack_64.c +++ b/arch/x86/kernel/dumpstack_64.c @@ -26,11 +26,12 @@ static const char * const exception_stack_names[] = { [ ESTACK_MCE ] = "#MC", [ ESTACK_VC ] = "#VC", [ ESTACK_VC2 ] = "#VC2", + [ ESTACK_IST ] = "#IST", }; const char *stack_type_name(enum stack_type type) { - BUILD_BUG_ON(N_EXCEPTION_STACKS != 6); + BUILD_BUG_ON(N_EXCEPTION_STACKS != ARRAY_SIZE(exception_stack_names)); if (type == STACK_TYPE_TASK) return "TASK"; @@ -89,6 +90,7 @@ struct estack_pages estack_pages[CEA_ESTACK_PAGES] ____cacheline_aligned = { EPAGERANGE(MCE), EPAGERANGE(VC), EPAGERANGE(VC2), + EPAGERANGE(IST), }; static __always_inline bool in_exception_stack(unsigned long *stack, struct stack_info *info) @@ -98,7 +100,7 @@ static __always_inline bool in_exception_stack(unsigned long *stack, struct stac struct pt_regs *regs; unsigned int k; - BUILD_BUG_ON(N_EXCEPTION_STACKS != 6); + BUILD_BUG_ON(N_EXCEPTION_STACKS != 7); begin = (unsigned long)__this_cpu_read(cea_exception_stacks); /* diff --git a/arch/x86/mm/cpu_entry_area.c b/arch/x86/mm/cpu_entry_area.c index 7316a8224259..62341cb819ab 100644 --- a/arch/x86/mm/cpu_entry_area.c +++ b/arch/x86/mm/cpu_entry_area.c @@ -148,6 +148,7 @@ static void __init percpu_setup_exception_stacks(unsigned int cpu) cea_map_stack(NMI); cea_map_stack(DB); cea_map_stack(MCE); + cea_map_stack(IST); if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) { if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) {