From patchwork Tue Apr 4 08:54:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nina Schoetterl-Glausch X-Patchwork-Id: 13199345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6ADFC761AF for ; Tue, 4 Apr 2023 08:55:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229488AbjDDIzS (ORCPT ); Tue, 4 Apr 2023 04:55:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233780AbjDDIzQ (ORCPT ); Tue, 4 Apr 2023 04:55:16 -0400 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA7CD2108; Tue, 4 Apr 2023 01:55:15 -0700 (PDT) Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3348V6RJ026565; Tue, 4 Apr 2023 08:55:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=/4helrcELGcFS7DjJWAzWaXoqP9vITarTFDdU0LBPHw=; b=Biq/F/ujeD7aPGuSg5Q6L0eP3KP7G++9fs9LEMoRVGtiOfuzabB0ANySu5IxoklI4ZIi LGSrG+qzBRJYJkl8yl55+ccdONpCDA33CRWsHaPRRY/KTH1AkOlAp8UrHyshkZQ7ay/8 3dlzKKkx9O3is4QtnvtK9M1/hzpgekDrfwGcWZnUispmN9swpk+9uINpIPvanWXEY8Yh 4EGCtN1SUJM3TmkaMS875wJeSFYAGl3vH4RBFfb7IgngfbC5gf/a1m7heinwf6tLBxS1 y/AUvxcFGs1FKdvCerzafyaa7dI71KaZ2XRhDFuOwrFdD1sv60zoh6Iv93DTFyat8s9X Rw== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3prgf0rff6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Apr 2023 08:55:15 +0000 Received: from m0098409.ppops.net (m0098409.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3348paCW013007; Tue, 4 Apr 2023 08:55:14 GMT Received: from ppma06ams.nl.ibm.com (66.31.33a9.ip4.static.sl-reverse.com [169.51.49.102]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3prgf0rfe3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Apr 2023 08:55:14 +0000 Received: from pps.filterd (ppma06ams.nl.ibm.com [127.0.0.1]) by ppma06ams.nl.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3341n3mr024634; Tue, 4 Apr 2023 08:55:12 GMT Received: from smtprelay05.fra02v.mail.ibm.com ([9.218.2.225]) by ppma06ams.nl.ibm.com (PPS) with ESMTPS id 3ppbvg2cnq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Apr 2023 08:55:12 +0000 Received: from smtpav07.fra02v.mail.ibm.com (smtpav07.fra02v.mail.ibm.com [10.20.54.106]) by smtprelay05.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3348t84J14484016 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Apr 2023 08:55:08 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CE0F620040; Tue, 4 Apr 2023 08:55:08 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 861BF2004B; Tue, 4 Apr 2023 08:55:08 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 4 Apr 2023 08:55:08 +0000 (GMT) From: Nina Schoetterl-Glausch To: Thomas Huth , Janosch Frank , Claudio Imbrenda Cc: Nina Schoetterl-Glausch , David Hildenbrand , kvm@vger.kernel.org, linux-s390@vger.kernel.org Subject: [kvm-unit-tests PATCH v5 2/3] s390x/spec_ex: Add test introducing odd address into PSW Date: Tue, 4 Apr 2023 10:54:52 +0200 Message-Id: <20230404085454.2709061-3-nsg@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230404085454.2709061-1-nsg@linux.ibm.com> References: <20230404085454.2709061-1-nsg@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: TAnsA_5gKkx9dkAqFV6KAZQNAyX39QPN X-Proofpoint-ORIG-GUID: o0h_RYXPKZWs--qxBoIRCnXP-FDyXH9O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-04_02,2023-04-03_03,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304040074 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Instructions on s390 must be halfword aligned. Introducing an odd instruction address into the PSW leads to a specification exception when attempting to execute the instruction at the odd address. Add a test for this. Acked-by: Janosch Frank Reviewed-by: Claudio Imbrenda Signed-off-by: Nina Schoetterl-Glausch Reviewed-by: Nico Boehr Tested-by: Nico Boehr --- s390x/spec_ex.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c index 2adc5996..494d94cc 100644 --- a/s390x/spec_ex.c +++ b/s390x/spec_ex.c @@ -88,12 +88,23 @@ static void expect_invalid_psw(struct psw psw) invalid_psw_expected = true; } +static void clear_invalid_psw(void) +{ + expected_psw = PSW(0, 0); + invalid_psw_expected = false; +} + static int check_invalid_psw(void) { /* Since the fixup sets this to false we check for false here. */ if (!invalid_psw_expected) { + /* + * Early exception recognition: pgm_int_id == 0. + * Late exception recognition: psw address has been + * incremented by pgm_int_id (unpredictable value) + */ if (expected_psw.mask == invalid_psw.mask && - expected_psw.addr == invalid_psw.addr) + expected_psw.addr == invalid_psw.addr - lowcore.pgm_int_id) return 0; report_fail("Wrong invalid PSW"); } else { @@ -112,6 +123,42 @@ static int psw_bit_12_is_1(void) return check_invalid_psw(); } +extern char misaligned_code_pre[]; +asm ( ".balign 2\n" +"misaligned_code_pre:\n" +" . = . + 1\n" +" larl %r0,0\n" +" br %r1\n" +); + +static int psw_odd_address(void) +{ + struct psw odd = PSW_WITH_CUR_MASK(((uint64_t)&misaligned_code_pre) + 1); + uint64_t executed_addr; + + expect_invalid_psw(odd); + fixup_psw.mask = extract_psw_mask(); + asm volatile ( "xgr %%r0,%%r0\n" + " larl %%r1,0f\n" + " stg %%r1,%[fixup_addr]\n" + " lpswe %[odd_psw]\n" + "0: lr %[executed_addr],%%r0\n" + : [fixup_addr] "=&T" (fixup_psw.addr), + [executed_addr] "=d" (executed_addr) + : [odd_psw] "Q" (odd) + : "cc", "%r0", "%r1", "memory" /* Compiler barrier like in load_psw */ + ); + + if (!executed_addr) { + return check_invalid_psw(); + } else { + assert(executed_addr == odd.addr); + clear_invalid_psw(); + report_fail("did not execute unaligned instructions"); + return 1; + } +} + /* A short PSW needs to have bit 12 set to be valid. */ static int short_psw_bit_12_is_0(void) { @@ -170,6 +217,7 @@ struct spec_ex_trigger { static const struct spec_ex_trigger spec_ex_triggers[] = { { "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw }, { "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw }, + { "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw }, { "bad_alignment", &bad_alignment, true, NULL }, { "not_even", ¬_even, true, NULL }, { NULL, NULL, false, NULL },