From patchwork Tue Apr 4 10:27:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 13199604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64F29C761A6 for ; Tue, 4 Apr 2023 10:56:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234939AbjDDK4F (ORCPT ); Tue, 4 Apr 2023 06:56:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234742AbjDDKzH (ORCPT ); Tue, 4 Apr 2023 06:55:07 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFBFB469C; Tue, 4 Apr 2023 03:54:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680605640; x=1712141640; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T7eEyAoHvwiW3Acg9V6KJ8qZ7RgqMyuTGxhG3JO7gws=; b=YSxjUTslFIJGg8U9fTbJPZNdUbixz49wM7ox1EXt/4jDc6zg5nfDB0e+ fdu4PHb/L8FC8qqmseUOB0JaqjvcySMZCG1rUmY8ZVWxgHf56A3UwOmAl ppnLtJGskQ5SQgDVlgo+0RduqQfRWCqPc2NgCDHqHYbLzU3I8lZCp7XXH 2xq/xzfwdSg47WF3mFec5M+BF2a0bPEFASijCDZfeKONNTprqm1DIKZ6D uZKDlQrTdhLLcMC49DxNkV7cc1Bu4IQfXs0PGUTuUCfGnZxExyZA4j3RM JEBl4qD1BXye1jPF+Ut8Xel8QhSyUOxo3PvpdOFEMnDD6bOMYzoS9fz5b w==; X-IronPort-AV: E=McAfee;i="6600,9927,10669"; a="330734166" X-IronPort-AV: E=Sophos;i="5.98,317,1673942400"; d="scan'208";a="330734166" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2023 03:53:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10669"; a="775597850" X-IronPort-AV: E=Sophos;i="5.98,317,1673942400"; d="scan'208";a="775597850" Received: from unknown (HELO fred..) ([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:05 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 24/33] x86/fred: disallow the swapgs instruction when FRED is enabled Date: Tue, 4 Apr 2023 03:27:07 -0700 Message-Id: <20230404102716.1795-25-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: "H. Peter Anvin (Intel)" The FRED architecture establishes the full supervisor/user through: 1) FRED event delivery swaps the value of the GS base address and that of the IA32_KERNEL_GS_BASE MSR. 2) ERETU swaps the value of the GS base address and that of the IA32_KERNEL_GS_BASE MSR. Thus, the swapgs instruction is disallowed when FRED is enabled, otherwise it causes #UD. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/kernel/process_64.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index a1aa74864c8b..2bea86073646 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -165,7 +165,8 @@ static noinstr unsigned long __rdgsbase_inactive(void) lockdep_assert_irqs_disabled(); - if (!cpu_feature_enabled(X86_FEATURE_XENPV)) { + if (!cpu_feature_enabled(X86_FEATURE_FRED) && + !cpu_feature_enabled(X86_FEATURE_XENPV)) { native_swapgs(); gsbase = rdgsbase(); native_swapgs(); @@ -190,7 +191,8 @@ static noinstr void __wrgsbase_inactive(unsigned long gsbase) { lockdep_assert_irqs_disabled(); - if (!cpu_feature_enabled(X86_FEATURE_XENPV)) { + if (!cpu_feature_enabled(X86_FEATURE_FRED) && + !cpu_feature_enabled(X86_FEATURE_XENPV)) { native_swapgs(); wrgsbase(gsbase); native_swapgs();