From patchwork Fri Apr 14 06:25:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Gao X-Patchwork-Id: 13211040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB56AC77B70 for ; Fri, 14 Apr 2023 06:26:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230003AbjDNG0U (ORCPT ); Fri, 14 Apr 2023 02:26:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230030AbjDNG0S (ORCPT ); Fri, 14 Apr 2023 02:26:18 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 435C16A42; Thu, 13 Apr 2023 23:26:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681453577; x=1712989577; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3v96gRV+sEhmeJkt6bLopXdOVIbOcXfn+M8hUk0aLec=; b=a16edSFrIgSJnGu0rB6WQQoEpFaIdU3Dbi8O3EOEM1AzOhL3WX19EXDL MPolO9O5tK6yq6rEgEdw8EuGAEzdz3MkamWeQiiF562ZAzMpO1bcDICsa U8Uk099+EXKRUiGuyTtL9jTS6KkO25Uq8ydU1ltU8WmJqeP90C9GiCWzO qAf70liVPIUSSpvj+pz8s4rJkfRCO1PiSoIZw7W/UYguc+PNZ9Hf2K9ZH 4NxfkrTYFPgmeZhFc1fxClLgXifGjv4pxm5zFLRW413Bu2kNekcftoWEI V2Qs8zxl1H9t1hvL5xQw4Aafj6g1jeYZIG8kqg2BE9xfUtKqD7AzV8WA8 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="341892723" X-IronPort-AV: E=Sophos;i="5.99,195,1677571200"; d="scan'208";a="341892723" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 23:26:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="935885827" X-IronPort-AV: E=Sophos;i="5.99,195,1677571200"; d="scan'208";a="935885827" Received: from spr.sh.intel.com ([10.239.53.106]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 23:26:13 -0700 From: Chao Gao To: kvm@vger.kernel.org Cc: Jiaan Lu , Zhang Chen , Chao Gao , Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 03/11] KVM: x86: Advertise BHI_CTRL support Date: Fri, 14 Apr 2023 14:25:24 +0800 Message-Id: <20230414062545.270178-4-chao.gao@intel.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230414062545.270178-1-chao.gao@intel.com> References: <20230414062545.270178-1-chao.gao@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Zhang Chen Add 100% kvm-only feature for BHI_CTRL because the kernel doesn't use it at all. BHI_CTRL is enumerated by CPUID.7.2.EDX[4]. If supported, BHI_DIS_S (bit 10) of IA32_SPEC_CTRL MSR can be used to enable BHI_DIS_S behavior. Note that KVM does not intercept guests' IA32_SPEC_CTRL MSR accesses after a non-zero is written to the MSR. Therefore, guests can already toggle the BHI_DIS_S bit if the host supports BHI_CTRL, and no extra code is needed to allow guests to toggle the bit. Signed-off-by: Zhang Chen Signed-off-by: Chao Gao Tested-by: Jiaan Lu --- arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/reverse_cpuid.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index f024c3ac2203..7cdd859d09a2 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -686,7 +686,7 @@ void kvm_set_cpu_caps(void) ); kvm_cpu_cap_init_kvm_defined(CPUID_7_2_EDX, - SF(RRSBA_CTRL) + SF(RRSBA_CTRL) | F(BHI_CTRL) ); kvm_cpu_cap_mask(CPUID_8000_0001_ECX, diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index 72bad8314a9c..e7e70c9aa384 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -50,6 +50,7 @@ enum kvm_only_cpuid_leafs { /* Intel-defined sub-features, CPUID level 0x00000007:2 (EDX) */ #define KVM_X86_FEATURE_RRSBA_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 2) +#define X86_FEATURE_BHI_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 4) struct cpuid_reg { u32 function;