@@ -210,22 +210,25 @@ static int setup_fdt(struct kvm *kvm)
riscv_irqchip_phandle));
_FDT(fdt_property(fdt, "ranges", NULL, 0));
- /* Virtio MMIO devices */
- dev_hdr = device__first_dev(DEVICE_BUS_MMIO);
- while (dev_hdr) {
- generate_mmio_fdt_nodes = dev_hdr->data;
- generate_mmio_fdt_nodes(fdt, dev_hdr,
- riscv__generate_irq_prop);
- dev_hdr = device__next_dev(dev_hdr);
- }
+ /* CoVE VMs do not support MMIO devices yet */
+ if (!kvm->cfg.arch.cove_vm) {
+ /* Virtio MMIO devices */
+ dev_hdr = device__first_dev(DEVICE_BUS_MMIO);
+ while (dev_hdr) {
+ generate_mmio_fdt_nodes = dev_hdr->data;
+ generate_mmio_fdt_nodes(fdt, dev_hdr,
+ riscv__generate_irq_prop);
+ dev_hdr = device__next_dev(dev_hdr);
+ }
- /* IOPORT devices */
- dev_hdr = device__first_dev(DEVICE_BUS_IOPORT);
- while (dev_hdr) {
- generate_mmio_fdt_nodes = dev_hdr->data;
- generate_mmio_fdt_nodes(fdt, dev_hdr,
- riscv__generate_irq_prop);
- dev_hdr = device__next_dev(dev_hdr);
+ /* IOPORT devices */
+ dev_hdr = device__first_dev(DEVICE_BUS_IOPORT);
+ while (dev_hdr) {
+ generate_mmio_fdt_nodes = dev_hdr->data;
+ generate_mmio_fdt_nodes(fdt, dev_hdr,
+ riscv__generate_irq_prop);
+ dev_hdr = device__next_dev(dev_hdr);
+ }
}
/* PCI host controller */