@@ -231,6 +231,8 @@ struct kvm_arch {
#define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 7
/* SMCCC filter initialized for the VM */
#define KVM_ARCH_FLAG_SMCCC_FILTER_CONFIGURED 8
+ /* PMUVer set by userspace for the VM */
+#define KVM_ARCH_FLAG_PMUVER_DIRTY 9
unsigned long flags;
/*
@@ -164,12 +164,6 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
set_default_spectre(kvm);
kvm_arm_init_hypercalls(kvm);
- /*
- * Initialise the default PMUver before there is a chance to
- * create an actual PMU.
- */
- kvm->arch.dfr0_pmuver.imp = kvm_arm_pmu_get_pmuver_limit();
-
return 0;
err_free_cpumask:
@@ -871,6 +871,8 @@ static bool pmu_irq_is_valid(struct kvm *kvm, int irq)
int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu)
{
+ u8 new_limit;
+
lockdep_assert_held(&kvm->arch.config_lock);
if (!arm_pmu) {
@@ -880,6 +882,22 @@ int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu)
}
kvm->arch.arm_pmu = arm_pmu;
+ new_limit = kvm_arm_pmu_get_pmuver_limit(kvm);
+
+ /*
+ * Reset the value of ID_AA64DFR0_EL1.PMUVer to the new limit value,
+ * unless the current value was set by userspace and is still a valid
+ * value for the new PMU.
+ */
+ if (!test_bit(KVM_ARCH_FLAG_PMUVER_DIRTY, &kvm->arch.flags)) {
+ kvm->arch.dfr0_pmuver.imp = new_limit;
+ return 0;
+ }
+
+ if (kvm->arch.dfr0_pmuver.imp > new_limit) {
+ kvm->arch.dfr0_pmuver.imp = new_limit;
+ clear_bit(KVM_ARCH_FLAG_PMUVER_DIRTY, &kvm->arch.flags);
+ }
return 0;
}
@@ -1049,13 +1067,9 @@ int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)
return -ENXIO;
}
-u8 kvm_arm_pmu_get_pmuver_limit(void)
+u8 kvm_arm_pmu_get_pmuver_limit(struct kvm *kvm)
{
- u64 tmp;
+ u8 host_pmuver = kvm->arch.arm_pmu ? kvm->arch.arm_pmu->pmuver : 0;
- tmp = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
- tmp = cpuid_feature_cap_perfmon_field(tmp,
- ID_AA64DFR0_EL1_PMUVer_SHIFT,
- ID_AA64DFR0_EL1_PMUVer_V3P5);
- return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), tmp);
+ return min_t(u8, host_pmuver, ID_AA64DFR0_EL1_PMUVer_V3P5);
}
@@ -1382,8 +1382,11 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
{
u8 pmuver, host_pmuver;
bool valid_pmu;
+ u64 current_val = read_id_reg(vcpu, rd);
+ int ret = -EINVAL;
- host_pmuver = kvm_arm_pmu_get_pmuver_limit();
+ mutex_lock(&vcpu->kvm->arch.config_lock);
+ host_pmuver = kvm_arm_pmu_get_pmuver_limit(vcpu->kvm);
/*
* Allow AA64DFR0_EL1.PMUver to be set from userspace as long
@@ -1393,26 +1396,31 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
*/
pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val);
if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver))
- return -EINVAL;
+ goto out;
valid_pmu = (pmuver != 0 && pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
/* Make sure view register and PMU support do match */
if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
- return -EINVAL;
+ goto out;
/* We can only differ with PMUver, and anything else is an error */
- val ^= read_id_reg(vcpu, rd);
+ val ^= current_val;
val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
if (val)
- return -EINVAL;
+ goto out;
- if (valid_pmu)
+ if (valid_pmu) {
vcpu->kvm->arch.dfr0_pmuver.imp = pmuver;
- else
+ set_bit(KVM_ARCH_FLAG_PMUVER_DIRTY, &vcpu->kvm->arch.flags);
+ } else
vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver;
- return 0;
+ ret = 0;
+out:
+ mutex_unlock(&vcpu->kvm->arch.config_lock);
+
+ return ret;
}
static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
@@ -1421,8 +1429,11 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
{
u8 perfmon, host_perfmon;
bool valid_pmu;
+ u64 current_val = read_id_reg(vcpu, rd);
+ int ret = -EINVAL;
- host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
+ mutex_lock(&vcpu->kvm->arch.config_lock);
+ host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit(vcpu->kvm));
/*
* Allow DFR0_EL1.PerfMon to be set from userspace as long as
@@ -1433,26 +1444,31 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), val);
if ((perfmon != ID_DFR0_EL1_PerfMon_IMPDEF && perfmon > host_perfmon) ||
(perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3))
- return -EINVAL;
+ goto out;
valid_pmu = (perfmon != 0 && perfmon != ID_DFR0_EL1_PerfMon_IMPDEF);
/* Make sure view register and PMU support do match */
if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
- return -EINVAL;
+ goto out;
/* We can only differ with PerfMon, and anything else is an error */
- val ^= read_id_reg(vcpu, rd);
+ val ^= current_val;
val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
if (val)
- return -EINVAL;
+ goto out;
- if (valid_pmu)
+ if (valid_pmu) {
vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon);
- else
+ set_bit(KVM_ARCH_FLAG_PMUVER_DIRTY, &vcpu->kvm->arch.flags);
+ } else
vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon);
- return 0;
+ ret = 0;
+out:
+ mutex_unlock(&vcpu->kvm->arch.config_lock);
+
+ return ret;
}
/*
@@ -95,7 +95,7 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
#define kvm_pmu_is_3p5(vcpu) \
(vcpu->kvm->arch.dfr0_pmuver.imp >= ID_AA64DFR0_EL1_PMUVer_V3P5)
-u8 kvm_arm_pmu_get_pmuver_limit(void);
+u8 kvm_arm_pmu_get_pmuver_limit(struct kvm *kvm);
int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu);
#else
@@ -164,7 +164,7 @@ static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {}
static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}
static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}
-static inline u8 kvm_arm_pmu_get_pmuver_limit(void)
+static inline u8 kvm_arm_pmu_get_pmuver_limit(struct kvm *kvm)
{
return 0;
}
Currently, KVM uses the sanitized value of ID_AA64DFR0_EL1.PMUVer as the default value and the limit value of this field for vCPUs with PMU configured. But, the sanitized value could be inappropriate for the vCPUs on some heterogeneous PMU systems, as arm64_ftr_bits for PMUVer is defined as FTR_EXACT with safe_val == 0 (if the ID_AA64DFR0_EL1.PMUVer of all PEs on the host is not uniform, the sanitized value will be 0). Use the PMUver of the guest's PMU (kvm->arch.arm_pmu->pmuver) as the default value and the limit value of ID_AA64DFR0_EL1.PMUVer for vCPUs with PMU configured. When the guest's PMU is switched to a different PMU, reset the value of ID_AA64DFR0_EL1.PMUVer for the vCPUs based on the new PMU, unless userspace has already modified the PMUVer and the value is still valid even with the new PMU. Signed-off-by: Reiji Watanabe <reijiw@google.com> --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/arm.c | 6 ---- arch/arm64/kvm/pmu-emul.c | 28 +++++++++++++----- arch/arm64/kvm/sys_regs.c | 48 ++++++++++++++++++++----------- include/kvm/arm_pmu.h | 4 +-- 5 files changed, 57 insertions(+), 31 deletions(-)