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Wed, 21 Jun 2023 23:55:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D4.mail.protection.outlook.com (10.167.241.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.21 via Frontend Transport; Wed, 21 Jun 2023 23:55:56 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 18:55:54 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 13/21] iommu/amd: Introduce vIOMMU command-line option Date: Wed, 21 Jun 2023 18:55:00 -0500 Message-ID: <20230621235508.113949-14-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|MN2PR12MB4285:EE_ X-MS-Office365-Filtering-Correlation-Id: 906e513c-5a50-4fcc-3e1e-08db72b30e17 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:56.3080 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 906e513c-5a50-4fcc-3e1e-08db72b30e17 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4285 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org To disable vIOMMU feature, specify option "amd_iommu=viommu_disable". Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 ++ drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/init.c | 10 ++++++++++ 3 files changed, 13 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index c9dfa4734801..a65d22384ab8 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -46,6 +46,8 @@ void amd_iommu_debugfs_setup(struct amd_iommu *iommu); static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {} #endif +extern bool amd_iommu_viommu; + /* Needed for interrupt remapping */ extern int amd_iommu_prepare(void); extern int amd_iommu_enable(void); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index aa16a7079b5c..019a9182df87 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -96,6 +96,7 @@ #define FEATURE_GAM_VAPIC (1ULL<<21) #define FEATURE_GIOSUP (1ULL<<48) #define FEATURE_EPHSUP (1ULL<<50) +#define FEATURE_VIOMMU (1ULL<<55) #define FEATURE_SNP (1ULL<<63) #define FEATURE_GATS_5LEVEL 1ULL diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 6a045a187971..4dd9f09e16c4 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -194,6 +194,9 @@ bool amdr_ivrs_remap_support __read_mostly; bool amd_iommu_force_isolation __read_mostly; +/* VIOMMU enabling flag */ +bool amd_iommu_viommu = true; + /* * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap * to know which ones are already in use. @@ -2154,6 +2157,9 @@ static void print_iommu_info(void) if (iommu->features & FEATURE_SNP) pr_cont(" SNP"); + if (iommu->features & FEATURE_VIOMMU) + pr_cont(" vIOMMU"); + pr_cont("\n"); } } @@ -2166,6 +2172,8 @@ static void print_iommu_info(void) pr_info("V2 page table enabled (Paging mode : %d level)\n", amd_iommu_gpt_level); } + if (amd_iommu_viommu) + pr_info("AMD-Vi: vIOMMU enabled\n"); } static int __init amd_iommu_init_pci(void) @@ -3402,6 +3410,8 @@ static int __init parse_amd_iommu_options(char *str) amd_iommu_pgtable = AMD_IOMMU_V1; } else if (strncmp(str, "pgtbl_v2", 8) == 0) { amd_iommu_pgtable = AMD_IOMMU_V2; + } else if (strncmp(str, "viommu_disable", 14) == 0) { + amd_iommu_viommu = false; } else { pr_notice("Unknown option - '%s'\n", str); }