From patchwork Sat Jun 24 17:41:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13291734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62D72EB64DC for ; Sat, 24 Jun 2023 17:42:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233203AbjFXRms (ORCPT ); Sat, 24 Jun 2023 13:42:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233184AbjFXRmo (ORCPT ); Sat, 24 Jun 2023 13:42:44 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4505A1FCE for ; Sat, 24 Jun 2023 10:42:41 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-9875c2d949eso245431666b.0 for ; Sat, 24 Jun 2023 10:42:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628559; x=1690220559; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6yG7uyZQhQuE8IRVfm1616U0ICNkMM4p4uOU/m5IL/M=; b=dxyHvFLOjiM5qIEukAG2xMl1n86ITsN2iybJyGEigjKJVlhy51cYS87u2DPnXQ31pC gHAkCCHkCYY16GPiyHKQbc3JgGIWt8KVZKMQ11bQMxI8wmbkhpXTrhSRIis7MvSzXzGA QqIQX7YU8zRGusA6i+PUsjOKGUGI5MyD+m9fQnHJoKgoqtbykvuvRgFuKcOrXiZ5wK82 d4+FrbU+wLhVnWAPZm65aY66PB+II/Npxd/kMcikCaDIXW9+qED/83zvrvxZ25rk5SV9 YL9Y823LfrKqEK09lhq7IjRqf8oiJ0Vir5S+qOmXMiSNmRx8hZhk6ngn/jDc60j75Spz ZjEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628559; x=1690220559; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6yG7uyZQhQuE8IRVfm1616U0ICNkMM4p4uOU/m5IL/M=; b=l0Wl1yyZWvk+tuN/Og9nWh6k9z7O5UM6rE6vnb8YCDnpwJrB+dIdxVgi63mYvSC6pN rf/MIQu6BooPNaNFlECpedLn7EQPs13/BVbcxhzrxUsLVyfiRNWRpubgVJxE7J7T+oKr LAXa7nq+1d/NSw/GIRSSVEvJGkrs62Bp3XgrmnjwfZECMpmtKyIO4Mj8uZJpvunnN0/K 7prKMAubavCnx1CmHZb8IF8x6XLLuFbzmY+Yuy1toxD2+RyQXHCKwC8SzsFW+DuMyMZC DaS4o8LkMAO37zLkqSIdJsjDz/syuWiXcD+dRb5xEX2LEWvvJo91BopcAbKDu3DhTZi5 j2+Q== X-Gm-Message-State: AC+VfDzd8P9CD6Hl3l5hNyyxlaBuDhGJ0Kp2dZeKw4qFc5Um2lb4j/aT wzv1F9KWJmILkLIVDcM++6XCrA== X-Google-Smtp-Source: ACHHUZ60zeHeS0keOdxvMmlIP6tQPqVFwiu+Q/14meF2x41zpcQ/taPA6Be68P7WOGnSc/Te+Ujdng== X-Received: by 2002:a17:907:360e:b0:96a:4ea0:a1e7 with SMTP id bk14-20020a170907360e00b0096a4ea0a1e7mr23798201ejc.50.1687628559647; Sat, 24 Jun 2023 10:42:39 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id t14-20020a170906948e00b009886aaeb722sm1109079ejx.137.2023.06.24.10.42.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:42:39 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 10/16] accel: Rename NVMM 'struct qemu_vcpu' -> AccelCPUState Date: Sat, 24 Jun 2023 19:41:15 +0200 Message-Id: <20230624174121.11508-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We want all accelerators to share the same opaque pointer in CPUState. Rename NVMM 'qemu_vcpu' as 'AccelCPUState'; directly use the typedef, remove unnecessary casts. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/i386/nvmm/nvmm-all.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index 90e9e0a5b2..e5ee4af084 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -26,7 +26,7 @@ #include -struct qemu_vcpu { +struct AccelCPUState { struct nvmm_vcpu vcpu; uint8_t tpr; bool stop; @@ -49,10 +49,10 @@ struct qemu_machine { static bool nvmm_allowed; static struct qemu_machine qemu_mach; -static struct qemu_vcpu * +static AccelCPUState * get_qemu_vcpu(CPUState *cpu) { - return (struct qemu_vcpu *)cpu->accel; + return cpu->accel; } static struct nvmm_machine * @@ -86,7 +86,7 @@ nvmm_set_registers(CPUState *cpu) { CPUX86State *env = cpu->env_ptr; struct nvmm_machine *mach = get_nvmm_mach(); - struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu); + AccelCPUState *qcpu = get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu = &qcpu->vcpu; struct nvmm_x64_state *state = vcpu->state; uint64_t bitmap; @@ -223,7 +223,7 @@ nvmm_get_registers(CPUState *cpu) { CPUX86State *env = cpu->env_ptr; struct nvmm_machine *mach = get_nvmm_mach(); - struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu); + AccelCPUState *qcpu = get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu = &qcpu->vcpu; X86CPU *x86_cpu = X86_CPU(cpu); struct nvmm_x64_state *state = vcpu->state; @@ -347,7 +347,7 @@ static bool nvmm_can_take_int(CPUState *cpu) { CPUX86State *env = cpu->env_ptr; - struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu); + AccelCPUState *qcpu = get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu = &qcpu->vcpu; struct nvmm_machine *mach = get_nvmm_mach(); @@ -372,7 +372,7 @@ nvmm_can_take_int(CPUState *cpu) static bool nvmm_can_take_nmi(CPUState *cpu) { - struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu); + AccelCPUState *qcpu = get_qemu_vcpu(cpu); /* * Contrary to INTs, NMIs always schedule an exit when they are @@ -395,7 +395,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) { CPUX86State *env = cpu->env_ptr; struct nvmm_machine *mach = get_nvmm_mach(); - struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu); + AccelCPUState *qcpu = get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu = &qcpu->vcpu; X86CPU *x86_cpu = X86_CPU(cpu); struct nvmm_x64_state *state = vcpu->state; @@ -478,7 +478,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) static void nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu); + AccelCPUState *qcpu = get_qemu_vcpu(cpu); CPUX86State *env = cpu->env_ptr; X86CPU *x86_cpu = X86_CPU(cpu); uint64_t tpr; @@ -565,7 +565,7 @@ static int nvmm_handle_rdmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu); + AccelCPUState *qcpu = get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu = &qcpu->vcpu; X86CPU *x86_cpu = X86_CPU(cpu); struct nvmm_x64_state *state = vcpu->state; @@ -610,7 +610,7 @@ static int nvmm_handle_wrmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu); + AccelCPUState *qcpu = get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu = &qcpu->vcpu; X86CPU *x86_cpu = X86_CPU(cpu); struct nvmm_x64_state *state = vcpu->state; @@ -686,7 +686,7 @@ nvmm_vcpu_loop(CPUState *cpu) { CPUX86State *env = cpu->env_ptr; struct nvmm_machine *mach = get_nvmm_mach(); - struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu); + AccelCPUState *qcpu = get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu = &qcpu->vcpu; X86CPU *x86_cpu = X86_CPU(cpu); struct nvmm_vcpu_exit *exit = vcpu->exit; @@ -892,7 +892,7 @@ static void nvmm_ipi_signal(int sigcpu) { if (current_cpu) { - struct qemu_vcpu *qcpu = get_qemu_vcpu(current_cpu); + AccelCPUState *qcpu = get_qemu_vcpu(current_cpu); #if NVMM_USER_VERSION >= 2 struct nvmm_vcpu *vcpu = &qcpu->vcpu; nvmm_vcpu_stop(vcpu); @@ -926,7 +926,7 @@ nvmm_init_vcpu(CPUState *cpu) struct nvmm_vcpu_conf_cpuid cpuid; struct nvmm_vcpu_conf_tpr tpr; Error *local_error = NULL; - struct qemu_vcpu *qcpu; + AccelCPUState *qcpu; int ret, err; nvmm_init_cpu_signals(); @@ -942,7 +942,7 @@ nvmm_init_vcpu(CPUState *cpu) } } - qcpu = g_malloc0(sizeof(*qcpu)); + qcpu = g_new0(AccelCPUState, 1); ret = nvmm_vcpu_create(mach, cpu->cpu_index, &qcpu->vcpu); if (ret == -1) { @@ -1023,7 +1023,7 @@ void nvmm_destroy_vcpu(CPUState *cpu) { struct nvmm_machine *mach = get_nvmm_mach(); - struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu); + AccelCPUState *qcpu = get_qemu_vcpu(cpu); nvmm_vcpu_destroy(mach, &qcpu->vcpu); g_free(cpu->accel);