| Message ID | 20230802164701.192791-5-guoren@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: Add Native/Paravirt/CNA qspinlock support | expand |
On 8/2/23 12:46, guoren@kernel.org wrote: > \ > diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h > new file mode 100644 > index 000000000000..c644a92d4548 > --- /dev/null > +++ b/arch/riscv/include/asm/spinlock.h > @@ -0,0 +1,17 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > + > +#ifndef __ASM_RISCV_SPINLOCK_H > +#define __ASM_RISCV_SPINLOCK_H > + > +#ifdef CONFIG_QUEUED_SPINLOCKS > +#define _Q_PENDING_LOOPS (1 << 9) > +#endif > + > +#ifdef CONFIG_QUEUED_SPINLOCKS You can merge the two "#ifdef CONFIG_QUEUED_SPINLOCKS" into single one to avoid the duplication. Cheers, Longman > +#include <asm/qspinlock.h> > +#include <asm/qrwlock.h> > +#else > +#include <asm-generic/spinlock.h> > +#endif > + > +#endif /* __ASM_RISCV_SPINLOCK_H */
On Sat, Aug 12, 2023 at 3:34 AM Waiman Long <longman@redhat.com> wrote: > > > On 8/2/23 12:46, guoren@kernel.org wrote: > > \ > > diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h > > new file mode 100644 > > index 000000000000..c644a92d4548 > > --- /dev/null > > +++ b/arch/riscv/include/asm/spinlock.h > > @@ -0,0 +1,17 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > + > > +#ifndef __ASM_RISCV_SPINLOCK_H > > +#define __ASM_RISCV_SPINLOCK_H > > + > > +#ifdef CONFIG_QUEUED_SPINLOCKS > > +#define _Q_PENDING_LOOPS (1 << 9) > > +#endif > > + > > +#ifdef CONFIG_QUEUED_SPINLOCKS > > You can merge the two "#ifdef CONFIG_QUEUED_SPINLOCKS" into single one > to avoid the duplication. Okay. > > Cheers, > Longman > > > +#include <asm/qspinlock.h> > > +#include <asm/qrwlock.h> > > +#else > > +#include <asm-generic/spinlock.h> > > +#endif > > + > > +#endif /* __ASM_RISCV_SPINLOCK_H */ >
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 93ff677d2be5..e89a3bea3dc1 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -438,6 +438,22 @@ config NODES_SHIFT Specify the maximum number of NUMA Nodes available on the target system. Increases memory reserved to accommodate various tables. +choice + prompt "RISC-V spinlock type" + default RISCV_TICKET_SPINLOCKS + +config RISCV_TICKET_SPINLOCKS + bool "Using ticket spinlock" + +config RISCV_QUEUED_SPINLOCKS + bool "Using queued spinlock" + depends on SMP && MMU + select ARCH_USE_QUEUED_SPINLOCKS + help + Make sure your micro arch LL/SC has a strong forward progress guarantee. + Otherwise, stay at ticket-lock. +endchoice + config RISCV_ALTERNATIVE bool depends on !XIP_KERNEL diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild index 504f8b7e72d4..a0dc85e4a754 100644 --- a/arch/riscv/include/asm/Kbuild +++ b/arch/riscv/include/asm/Kbuild @@ -2,10 +2,11 @@ generic-y += early_ioremap.h generic-y += flat.h generic-y += kvm_para.h +generic-y += mcs_spinlock.h generic-y += parport.h -generic-y += spinlock.h generic-y += spinlock_types.h generic-y += qrwlock.h generic-y += qrwlock_types.h +generic-y += qspinlock.h generic-y += user.h generic-y += vmlinux.lds.h diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 2f4726d3cfcc..d12231d752a4 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -11,12 +11,36 @@ #include <asm/barrier.h> #include <asm/fence.h> +static inline ulong __xchg16_relaxed(ulong new, void *ptr) +{ + ulong ret, tmp; + ulong shif = ((ulong)ptr & 2) ? 16 : 0; + ulong mask = 0xffff << shif; + ulong *__ptr = (ulong *)((ulong)ptr & ~2); + + __asm__ __volatile__ ( + "0: lr.w %0, %2\n" + " and %1, %0, %z3\n" + " or %1, %1, %z4\n" + " sc.w %1, %1, %2\n" + " bnez %1, 0b\n" + : "=&r" (ret), "=&r" (tmp), "+A" (*__ptr) + : "rJ" (~mask), "rJ" (new << shif) + : "memory"); + + return (ulong)((ret & mask) >> shif); +} + #define __xchg_relaxed(ptr, new, size) \ ({ \ __typeof__(ptr) __ptr = (ptr); \ __typeof__(new) __new = (new); \ __typeof__(*(ptr)) __ret; \ switch (size) { \ + case 2: \ + __ret = (__typeof__(*(ptr))) \ + __xchg16_relaxed((ulong)__new, __ptr); \ + break; \ case 4: \ __asm__ __volatile__ ( \ " amoswap.w %0, %2, %1\n" \ diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h new file mode 100644 index 000000000000..c644a92d4548 --- /dev/null +++ b/arch/riscv/include/asm/spinlock.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __ASM_RISCV_SPINLOCK_H +#define __ASM_RISCV_SPINLOCK_H + +#ifdef CONFIG_QUEUED_SPINLOCKS +#define _Q_PENDING_LOOPS (1 << 9) +#endif + +#ifdef CONFIG_QUEUED_SPINLOCKS +#include <asm/qspinlock.h> +#include <asm/qrwlock.h> +#else +#include <asm-generic/spinlock.h> +#endif + +#endif /* __ASM_RISCV_SPINLOCK_H */