From patchwork Fri Sep 1 05:30:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 13372062 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5C69CA0FE8 for ; Fri, 1 Sep 2023 05:59:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344263AbjIAF73 (ORCPT ); Fri, 1 Sep 2023 01:59:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229829AbjIAF73 (ORCPT ); Fri, 1 Sep 2023 01:59:29 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3C2A10C0 for ; Thu, 31 Aug 2023 22:59:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693547966; x=1725083966; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cYxBFAMtro4zbkcrtr3LvUksDBEPZ7yuMe4iZR87FMY=; b=mXQxBf4IMp9pz+FHtmeEy8RanwdKJZoM9hTuiInojr2xgnckmg34rzCn SYqVzbaFqyXOgyERqoMRTgvSC8V4qfbh1HLoVjq6hG/CmRTS5I+3UQZLF Uix59IB94SKsfv/QmxVcp0KnhISPyxjIs9mFwRbXBJRgTzyKSeGIwMqzc M04wprWER6wZW5UkGwTg/cS8Wd5o6y/XVs0vz6KNY/yZfCRKPVr3ZjG+v Rg6D8dboDR3d/yeHV+IyflIkWG3RFXTjNZAHkL4e+WaXl3PDgAHnqn5FC BP9PGqVJ8CRYjHxynH4uSYRazporGJFAYxHE57iFDw5O+UN7hn/BYZO38 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="356456633" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="356456633" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2023 22:59:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="739816164" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="739816164" Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga002.jf.intel.com with ESMTP; 31 Aug 2023 22:59:25 -0700 From: Xin Li To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, chao.gao@intel.com, hpa@zytor.com, xiaoyao.li@intel.com, weijiang.yang@intel.com Subject: [PATCH 2/4] target/i386: mark CR4.FRED not reserved Date: Thu, 31 Aug 2023 22:30:20 -0700 Message-Id: <20230901053022.18672-3-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230901053022.18672-1-xin3.li@intel.com> References: <20230901053022.18672-1-xin3.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The CR4.FRED bit, i.e., CR4[32], is no longer a reserved bit when FRED is exposed to guests, otherwise it is still a reserved bit. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 064decbc85..924819a64c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -262,6 +262,12 @@ typedef enum X86Seg { #define CR4_PKE_MASK (1U << 22) #define CR4_PKS_MASK (1U << 24) +#ifdef TARGET_X86_64 +#define CR4_FRED_MASK (1ULL << 32) +#else +#define CR4_FRED_MASK 0 +#endif + #define CR4_RESERVED_MASK \ (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ @@ -269,7 +275,8 @@ typedef enum X86Seg { | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \ | CR4_LA57_MASK \ | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ - | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK)) + | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK \ + | CR4_FRED_MASK)) #define DR6_BD (1 << 13) #define DR6_BS (1 << 14) @@ -2481,6 +2488,9 @@ static inline uint64_t cr4_reserved_bits(CPUX86State *env) if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { reserved_bits |= CR4_PKS_MASK; } + if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED)) { + reserved_bits |= CR4_FRED_MASK; + } return reserved_bits; }