| Message ID | 20230901072809.640175-5-xiong.y.zhang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Upgrade vPMU version to 5 | expand |
On 1/9/2023 3:28 pm, Xiong Zhang wrote: > Arch PMU v4 introduces a new MSR, IA32_PERF_GLOBAL_INUSE. It provides > as "InUse" bit for each GP counter and fixed counter in processor. > Additionally PMI InUse[bit 63] indicates if the PMI mechanism has been > configured. > > Each bit's definition references Architectural Performance Monitoring > Version 4 section of SDM. > > Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> > --- > arch/x86/include/asm/msr-index.h | 4 +++ > arch/x86/kvm/vmx/pmu_intel.c | 58 ++++++++++++++++++++++++++++++++ > 2 files changed, 62 insertions(+) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 7c8cf6b53a76..31bb425899fb 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -1036,6 +1036,7 @@ > #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f > #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 > #define MSR_CORE_PERF_GLOBAL_STATUS_SET 0x00000391 > +#define MSR_CORE_PERF_GLOBAL_INUSE 0x00000392 > > #define MSR_PERF_METRICS 0x00000329 > > @@ -1048,6 +1049,9 @@ > #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 > #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) > > +/* PERF_GLOBAL_INUSE bits */ > +#define MSR_CORE_PERF_GLOBAL_INUSE_PMI BIT_ULL(63) > + > /* Geode defined MSRs */ > #define MSR_GEODE_BUSCONT_CONF0 0x00001900 > > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c > index b25df421cd75..46363ac82a79 100644 > --- a/arch/x86/kvm/vmx/pmu_intel.c > +++ b/arch/x86/kvm/vmx/pmu_intel.c > @@ -207,6 +207,7 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) > case MSR_CORE_PERF_FIXED_CTR_CTRL: > return kvm_pmu_has_perf_global_ctrl(pmu); > case MSR_CORE_PERF_GLOBAL_STATUS_SET: > + case MSR_CORE_PERF_GLOBAL_INUSE: > return vcpu_to_pmu(vcpu)->version >= 4; > case MSR_IA32_PEBS_ENABLE: > ret = vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT; > @@ -347,6 +348,58 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu, > return true; > } > > +static u64 intel_pmu_global_inuse_emulation(struct kvm_pmu *pmu) > +{ > + u64 data = 0; > + int i; > + > + for (i = 0; i < pmu->nr_arch_gp_counters; i++) { > + struct kvm_pmc *pmc = &pmu->gp_counters[i]; > + > + /* > + * IA32_PERF_GLOBAL_INUSE.PERFEVTSELn_InUse[bit n]: This bit > + * reflects the logical state of (IA32_PERFEVTSELn[7:0]), > + * n < CPUID.0AH.EAX[15:8]. > + */ > + if (pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT) > + data |= 1 << i; > + /* > + * IA32_PERF_GLOBAL_INUSE.PMI_InUse[bit 63]: This bit is set if > + * IA32_PERFEVTSELn.INT[bit 20], n < CPUID.0AH.EAX[15:8] is set. > + */ > + if (pmc->eventsel & ARCH_PERFMON_EVENTSEL_INT) > + data |= MSR_CORE_PERF_GLOBAL_INUSE_PMI; If this bit is already set, there is no need to repeat it to avoid wasting cycles. > + } > + > + for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { > + /* > + * IA32_PERF_GLOBAL_INUSE.FCi_InUse[bit (i + 32)]: This bit > + * reflects the logical state of > + * IA32_FIXED_CTR_CTRL[i * 4 + 1, i * 4] != 0 > + */ > + if (pmu->fixed_ctr_ctrl & > + intel_fixed_bits_by_idx(i, INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER)) > + data |= 1ULL << (i + INTEL_PMC_IDX_FIXED); > + /* > + * IA32_PERF_GLOBAL_INUSE.PMI_InUse[bit 63]: This bit is set if > + * IA32_FIXED_CTR_CTRL.ENi_PMI, i = 0, 1, 2 is set. > + */ > + if (pmu->fixed_ctr_ctrl & > + intel_fixed_bits_by_idx(i, INTEL_FIXED_0_ENABLE_PMI)) > + data |= MSR_CORE_PERF_GLOBAL_INUSE_PMI; > + } > + > + /* > + * IA32_PERF_GLOBAL_INUSE.PMI_InUse[bit 63]: This bit is set if > + * any IA32_PEBS_ENABLES bit is set, which enables PEBS for a GP or > + * fixed counter. > + */ > + if (pmu->pebs_enable) > + data |= MSR_CORE_PERF_GLOBAL_INUSE_PMI; > + > + return data; > +} > + > static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > { > struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); > @@ -360,6 +413,9 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > case MSR_CORE_PERF_GLOBAL_STATUS_SET: > msr_info->data = 0; > break; > + case MSR_CORE_PERF_GLOBAL_INUSE: > + msr_info->data = intel_pmu_global_inuse_emulation(pmu); > + break; > case MSR_IA32_PEBS_ENABLE: > msr_info->data = pmu->pebs_enable; > break; > @@ -409,6 +465,8 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > if (pmu->fixed_ctr_ctrl != data) > reprogram_fixed_counters(pmu, data); > break; > + case MSR_CORE_PERF_GLOBAL_INUSE: > + return 1; /* RO MSR */ Is msrs_to_save_pmu[] updated? > case MSR_IA32_PEBS_ENABLE: > if (data & pmu->pebs_enable_mask) > return 1;
> On 1/9/2023 3:28 pm, Xiong Zhang wrote: > > Arch PMU v4 introduces a new MSR, IA32_PERF_GLOBAL_INUSE. It provides > > as "InUse" bit for each GP counter and fixed counter in processor. > > Additionally PMI InUse[bit 63] indicates if the PMI mechanism has been > > configured. > > > > Each bit's definition references Architectural Performance Monitoring > > Version 4 section of SDM. > > > > Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> > > --- > > arch/x86/include/asm/msr-index.h | 4 +++ > > arch/x86/kvm/vmx/pmu_intel.c | 58 > ++++++++++++++++++++++++++++++++ > > 2 files changed, 62 insertions(+) > > > > diff --git a/arch/x86/include/asm/msr-index.h > > b/arch/x86/include/asm/msr-index.h > > index 7c8cf6b53a76..31bb425899fb 100644 > > --- a/arch/x86/include/asm/msr-index.h > > +++ b/arch/x86/include/asm/msr-index.h > > @@ -1036,6 +1036,7 @@ > > #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f > > #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 > > #define MSR_CORE_PERF_GLOBAL_STATUS_SET 0x00000391 > > +#define MSR_CORE_PERF_GLOBAL_INUSE 0x00000392 > > > > #define MSR_PERF_METRICS 0x00000329 > > > > @@ -1048,6 +1049,9 @@ > > #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT > 63 > > #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD > (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) > > > > +/* PERF_GLOBAL_INUSE bits */ > > +#define MSR_CORE_PERF_GLOBAL_INUSE_PMI > BIT_ULL(63) > > + > > /* Geode defined MSRs */ > > #define MSR_GEODE_BUSCONT_CONF0 0x00001900 > > > > diff --git a/arch/x86/kvm/vmx/pmu_intel.c > > b/arch/x86/kvm/vmx/pmu_intel.c index b25df421cd75..46363ac82a79 100644 > > --- a/arch/x86/kvm/vmx/pmu_intel.c > > +++ b/arch/x86/kvm/vmx/pmu_intel.c > > @@ -207,6 +207,7 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, > u32 msr) > > case MSR_CORE_PERF_FIXED_CTR_CTRL: > > return kvm_pmu_has_perf_global_ctrl(pmu); > > case MSR_CORE_PERF_GLOBAL_STATUS_SET: > > + case MSR_CORE_PERF_GLOBAL_INUSE: > > return vcpu_to_pmu(vcpu)->version >= 4; > > case MSR_IA32_PEBS_ENABLE: > > ret = vcpu_get_perf_capabilities(vcpu) & > PERF_CAP_PEBS_FORMAT; @@ > > -347,6 +348,58 @@ static bool intel_pmu_handle_lbr_msrs_access(struct > kvm_vcpu *vcpu, > > return true; > > } > > > > +static u64 intel_pmu_global_inuse_emulation(struct kvm_pmu *pmu) { > > + u64 data = 0; > > + int i; > > + > > + for (i = 0; i < pmu->nr_arch_gp_counters; i++) { > > + struct kvm_pmc *pmc = &pmu->gp_counters[i]; > > + > > + /* > > + * IA32_PERF_GLOBAL_INUSE.PERFEVTSELn_InUse[bit n]: This > bit > > + * reflects the logical state of (IA32_PERFEVTSELn[7:0]), > > + * n < CPUID.0AH.EAX[15:8]. > > + */ > > + if (pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT) > > + data |= 1 << i; > > + /* > > + * IA32_PERF_GLOBAL_INUSE.PMI_InUse[bit 63]: This bit is set > if > > + * IA32_PERFEVTSELn.INT[bit 20], n < CPUID.0AH.EAX[15:8] is > set. > > + */ > > + if (pmc->eventsel & ARCH_PERFMON_EVENTSEL_INT) > > + data |= MSR_CORE_PERF_GLOBAL_INUSE_PMI; > > If this bit is already set, there is no need to repeat it to avoid wasting cycles. Get it. > > > + } > > + > > + for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { > > + /* > > + * IA32_PERF_GLOBAL_INUSE.FCi_InUse[bit (i + 32)]: This bit > > + * reflects the logical state of > > + * IA32_FIXED_CTR_CTRL[i * 4 + 1, i * 4] != 0 > > + */ > > + if (pmu->fixed_ctr_ctrl & > > + intel_fixed_bits_by_idx(i, INTEL_FIXED_0_KERNEL | > INTEL_FIXED_0_USER)) > > + data |= 1ULL << (i + INTEL_PMC_IDX_FIXED); > > + /* > > + * IA32_PERF_GLOBAL_INUSE.PMI_InUse[bit 63]: This bit is set > if > > + * IA32_FIXED_CTR_CTRL.ENi_PMI, i = 0, 1, 2 is set. > > + */ > > + if (pmu->fixed_ctr_ctrl & > > + intel_fixed_bits_by_idx(i, INTEL_FIXED_0_ENABLE_PMI)) > > + data |= MSR_CORE_PERF_GLOBAL_INUSE_PMI; > > + } > > + > > + /* > > + * IA32_PERF_GLOBAL_INUSE.PMI_InUse[bit 63]: This bit is set if > > + * any IA32_PEBS_ENABLES bit is set, which enables PEBS for a GP or > > + * fixed counter. > > + */ > > + if (pmu->pebs_enable) > > + data |= MSR_CORE_PERF_GLOBAL_INUSE_PMI; > > + > > + return data; > > +} > > + > > static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data > *msr_info) > > { > > struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -360,6 +413,9 @@ > static > > int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > > case MSR_CORE_PERF_GLOBAL_STATUS_SET: > > msr_info->data = 0; > > break; > > + case MSR_CORE_PERF_GLOBAL_INUSE: > > + msr_info->data = intel_pmu_global_inuse_emulation(pmu); > > + break; > > case MSR_IA32_PEBS_ENABLE: > > msr_info->data = pmu->pebs_enable; > > break; > > @@ -409,6 +465,8 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, > struct msr_data *msr_info) > > if (pmu->fixed_ctr_ctrl != data) > > reprogram_fixed_counters(pmu, data); > > break; > > + case MSR_CORE_PERF_GLOBAL_INUSE: > > + return 1; /* RO MSR */ > > Is msrs_to_save_pmu[] updated? I will add it and GLOBAL_STATUS_SET in next version. thanks > > > case MSR_IA32_PEBS_ENABLE: > > if (data & pmu->pebs_enable_mask) > > return 1;
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 7c8cf6b53a76..31bb425899fb 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1036,6 +1036,7 @@ #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 #define MSR_CORE_PERF_GLOBAL_STATUS_SET 0x00000391 +#define MSR_CORE_PERF_GLOBAL_INUSE 0x00000392 #define MSR_PERF_METRICS 0x00000329 @@ -1048,6 +1049,9 @@ #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) +/* PERF_GLOBAL_INUSE bits */ +#define MSR_CORE_PERF_GLOBAL_INUSE_PMI BIT_ULL(63) + /* Geode defined MSRs */ #define MSR_GEODE_BUSCONT_CONF0 0x00001900 diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index b25df421cd75..46363ac82a79 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -207,6 +207,7 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) case MSR_CORE_PERF_FIXED_CTR_CTRL: return kvm_pmu_has_perf_global_ctrl(pmu); case MSR_CORE_PERF_GLOBAL_STATUS_SET: + case MSR_CORE_PERF_GLOBAL_INUSE: return vcpu_to_pmu(vcpu)->version >= 4; case MSR_IA32_PEBS_ENABLE: ret = vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT; @@ -347,6 +348,58 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu, return true; } +static u64 intel_pmu_global_inuse_emulation(struct kvm_pmu *pmu) +{ + u64 data = 0; + int i; + + for (i = 0; i < pmu->nr_arch_gp_counters; i++) { + struct kvm_pmc *pmc = &pmu->gp_counters[i]; + + /* + * IA32_PERF_GLOBAL_INUSE.PERFEVTSELn_InUse[bit n]: This bit + * reflects the logical state of (IA32_PERFEVTSELn[7:0]), + * n < CPUID.0AH.EAX[15:8]. + */ + if (pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT) + data |= 1 << i; + /* + * IA32_PERF_GLOBAL_INUSE.PMI_InUse[bit 63]: This bit is set if + * IA32_PERFEVTSELn.INT[bit 20], n < CPUID.0AH.EAX[15:8] is set. + */ + if (pmc->eventsel & ARCH_PERFMON_EVENTSEL_INT) + data |= MSR_CORE_PERF_GLOBAL_INUSE_PMI; + } + + for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { + /* + * IA32_PERF_GLOBAL_INUSE.FCi_InUse[bit (i + 32)]: This bit + * reflects the logical state of + * IA32_FIXED_CTR_CTRL[i * 4 + 1, i * 4] != 0 + */ + if (pmu->fixed_ctr_ctrl & + intel_fixed_bits_by_idx(i, INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER)) + data |= 1ULL << (i + INTEL_PMC_IDX_FIXED); + /* + * IA32_PERF_GLOBAL_INUSE.PMI_InUse[bit 63]: This bit is set if + * IA32_FIXED_CTR_CTRL.ENi_PMI, i = 0, 1, 2 is set. + */ + if (pmu->fixed_ctr_ctrl & + intel_fixed_bits_by_idx(i, INTEL_FIXED_0_ENABLE_PMI)) + data |= MSR_CORE_PERF_GLOBAL_INUSE_PMI; + } + + /* + * IA32_PERF_GLOBAL_INUSE.PMI_InUse[bit 63]: This bit is set if + * any IA32_PEBS_ENABLES bit is set, which enables PEBS for a GP or + * fixed counter. + */ + if (pmu->pebs_enable) + data |= MSR_CORE_PERF_GLOBAL_INUSE_PMI; + + return data; +} + static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -360,6 +413,9 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_CORE_PERF_GLOBAL_STATUS_SET: msr_info->data = 0; break; + case MSR_CORE_PERF_GLOBAL_INUSE: + msr_info->data = intel_pmu_global_inuse_emulation(pmu); + break; case MSR_IA32_PEBS_ENABLE: msr_info->data = pmu->pebs_enable; break; @@ -409,6 +465,8 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) if (pmu->fixed_ctr_ctrl != data) reprogram_fixed_counters(pmu, data); break; + case MSR_CORE_PERF_GLOBAL_INUSE: + return 1; /* RO MSR */ case MSR_IA32_PEBS_ENABLE: if (data & pmu->pebs_enable_mask) return 1;
Arch PMU v4 introduces a new MSR, IA32_PERF_GLOBAL_INUSE. It provides as "InUse" bit for each GP counter and fixed counter in processor. Additionally PMI InUse[bit 63] indicates if the PMI mechanism has been configured. Each bit's definition references Architectural Performance Monitoring Version 4 section of SDM. Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> --- arch/x86/include/asm/msr-index.h | 4 +++ arch/x86/kvm/vmx/pmu_intel.c | 58 ++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+)