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[kvm-unit-tests,3/6] x86: pmu: PERF_GLOBAL_STATUS_SET MSR verification for vPMU v4

Message ID 20230901074052.640296-4-xiong.y.zhang@intel.com (mailing list archive)
State New, archived
Headers show
Series vPMU v5 test case | expand

Commit Message

Zhang, Xiong Y Sept. 1, 2023, 7:40 a.m. UTC 
The IA32_PERF_GLOBAL_STATUS_SET MSR is introduced with arch PMU v4.
It allows software to set individual bits in IA32_PERF_GLOBAL_STATUS
MSR.

This commit adds the test case for this MSR. When global status is
cleared at counter overflow, guest write PERF_GLOBAL_STATUS_SET
MSR to set the counter overflow bit, then check this counter's
overflow bit in IA32_PERF_GLOABAL_STATUS MSR.

Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
---
 lib/x86/msr.h | 1 +
 x86/pmu.c     | 8 ++++++++
 2 files changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/lib/x86/msr.h b/lib/x86/msr.h
index 9748436..63b8539 100644
--- a/lib/x86/msr.h
+++ b/lib/x86/msr.h
@@ -429,6 +429,7 @@ 
 #define MSR_CORE_PERF_GLOBAL_STATUS	0x0000038e
 #define MSR_CORE_PERF_GLOBAL_CTRL	0x0000038f
 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x00000390
+#define MSR_CORE_PERF_GLOBAL_STATUS_SET	0x00000391
 
 /* PERF_GLOBAL_OVF_CTRL bits */
 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_LBR_FREEZE  (1ULL << 58)
diff --git a/x86/pmu.c b/x86/pmu.c
index 72c2c9c..a171e9e 100644
--- a/x86/pmu.c
+++ b/x86/pmu.c
@@ -350,6 +350,14 @@  static void check_counter_overflow(void)
 		status = rdmsr(pmu.msr_global_status);
 		report(!(status & (1ull << idx)), "status clear-%d", i);
 		report(check_irq() == (i % 2), "irq-%d", i);
+		if (pmu.version >= 4) {
+			wrmsr(MSR_CORE_PERF_GLOBAL_STATUS_SET, 1ull << idx);
+			status = rdmsr(pmu.msr_global_status);
+			report(status & (1ull << idx), "status set-%d", i);
+			wrmsr(pmu.msr_global_status_clr, 1ull << idx);
+			status = rdmsr(pmu.msr_global_status);
+			report(!(status & (1ull << idx)), "status set clear-%d", i);
+		}
 	}
 
 	report_prefix_pop();