Message ID | 20231009112401.1060447-8-dtatulea@nvidia.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Tsirkin" <mst@redhat.com>, Jason Wang <jasowang@redhat.com>, Eugenio Perez Martin <eperezma@redhat.com>, Si-Wei Liu <si-wei.liu@oracle.com>, Saeed Mahameed <saeedm@nvidia.com>, Leon Romanovsky <leon@kernel.org>, <virtualization@lists.linux-foundation.org> CC: Dragos Tatulea <dtatulea@nvidia.com>, <kvm@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Parav Pandit <parav@nvidia.com>, Xuan Zhuo <xuanzhuo@linux.alibaba.com> Subject: [PATCH vhost v3 07/16] vdpa/mlx5: Take cvq iotlb lock during refresh Date: Mon, 9 Oct 2023 14:23:52 +0300 Message-ID: <20231009112401.1060447-8-dtatulea@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231009112401.1060447-1-dtatulea@nvidia.com> References: <20231009112401.1060447-1-dtatulea@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD5:EE_|PH0PR12MB7887:EE_ X-MS-Office365-Filtering-Correlation-Id: df07ddcd-29a2-4475-2fd4-08dbc8ba5fa6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: E6pNu0ufCgR5HLXjXutWH4pe+K8PpVLKlbzyh54pM8878HddeSxfdOTqzNV+nefhz5CtLrhzxUx0PEVIsvtWW2dxHaxwt4r5+hGpT9bHrbDipx0kxZwoMF7oTSZ2ruScJQ9mefReN+sOE4ZZKYDGZzrkJKMstKlJjBGwnv7Ao+OLF8fHXsd0pJpY2lAH1/3p5oRbH6TISgFhAxG9gJz5z7THUNjvuIBkqu2PG+KDtLCtm789BquLH9fkped+rwn/tbC57XkXiZAnuUPbR1OGoakCuF70AuNFiacCblskNJIj1Bi/hwU/edzEVhTCzkyIm1JVHJvMd5iCdO3OGXs6RLwlDqmzUajFlzth4zsvJEDXP8S0OY3/uD3LjsN4BdgDXNAq9mSoZqbFR7P7FNBxOpF9xT8HOdc4Ox0rvkwuUPDfBFydEBxIykhGQFFvKFNBNDQHZE03zqjlYajYPmyGIWQelJbv9nUWvEAhvYJREUFHBdRPkW/ULUPq4r8TBOgSVg45x75Q3G++ymH+xgCWKk4Ew4lbir6V5fGDhsFNsdVIIzk7xiP21mswRCB/TaQpmJ4CKJyeb1o1bLBq+TFuLbbK3TlJVYdQ+jtRJPPpXKoY3hRrLF89aXRaOWfasl26A+knSDfjeExepZ+la/O/A6b3PMG4JXbdO6AUr/EwLR4Id4au7gOkNxyUXxGPc77YmF4vTUCLsEWSRIq9HlpfLlAjOn52CuX7d7zEj5Zy8pTc/CFJ1iTV61BRu7FWkpJ7n+AIOK6fpaBjwyyU/gp4u+YBI8m3Gow64odmZHc5XWo= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(396003)(376002)(346002)(230922051799003)(451199024)(64100799003)(1800799009)(186009)(82310400011)(40470700004)(36840700001)(46966006)(1076003)(478600001)(966005)(2616005)(66574015)(2906002)(47076005)(336012)(426003)(26005)(83380400001)(5660300002)(110136005)(54906003)(70206006)(8936002)(4326008)(8676002)(41300700001)(70586007)(316002)(40480700001)(82740400003)(356005)(7636003)(36860700001)(36756003)(40460700003)(86362001)(6666004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2023 11:24:59.5224 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df07ddcd-29a2-4475-2fd4-08dbc8ba5fa6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7887 Precedence: bulk List-ID: <kvm.vger.kernel.org> X-Mailing-List: kvm@vger.kernel.org |
Series |
vdpa: Add support for vq descriptor mappings
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expand
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diff --git a/drivers/vdpa/mlx5/core/mr.c b/drivers/vdpa/mlx5/core/mr.c index fcb6ae32e9ed..587300e7c18e 100644 --- a/drivers/vdpa/mlx5/core/mr.c +++ b/drivers/vdpa/mlx5/core/mr.c @@ -590,11 +590,19 @@ int mlx5_vdpa_update_cvq_iotlb(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb, unsigned int asid) { + int err; + if (mvdev->group2asid[MLX5_VDPA_CVQ_GROUP] != asid) return 0; + spin_lock(&mvdev->cvq.iommu_lock); + prune_iotlb(mvdev); - return dup_iotlb(mvdev, iotlb); + err = dup_iotlb(mvdev, iotlb); + + spin_unlock(&mvdev->cvq.iommu_lock); + + return err; } int mlx5_vdpa_create_dma_mr(struct mlx5_vdpa_dev *mvdev)