| Message ID | 20231024075748.1675382-4-dapeng1.mi@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix PMU test failures on Sapphire Rapids | expand |
diff --git a/x86/pmu.c b/x86/pmu.c index 7443fdab5c8a..1bebf493d4a4 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -254,7 +254,7 @@ static void check_fixed_counters(void) static void check_counters_many(void) { - pmu_counter_t cnt[10]; + pmu_counter_t cnt[64]; int i, n; for (i = 0, n = 0; n < pmu.nr_gp_counters; i++) {
Considering there are already 8 GP counters and 4 fixed counters on latest Intel CPUs, like Sapphire Rapids. The original cnt array length 10 is definitely not enough to cover all supported PMU counters on these new CPUs and it would cause PMU counter validation failures. It's probably more and more GP and fixed counters are introduced in the future and then directly extends the cnt array length to 64. Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> --- x86/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)