From patchwork Tue Oct 24 09:03:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13434105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C5BDC00A8F for ; Tue, 24 Oct 2023 08:55:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233456AbjJXIzB (ORCPT ); Tue, 24 Oct 2023 04:55:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234055AbjJXIyp (ORCPT ); Tue, 24 Oct 2023 04:54:45 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E49FCC0 for ; Tue, 24 Oct 2023 01:54:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698137654; x=1729673654; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7WFJedNLWzB+pwTLUI8IYFyCdnkJ0teulhLYoRGpexs=; b=NoTbblBDOMZM5d24QYF+dQK5L4bQvBh/4DuupReWZfyQNBY2SjH8xwkO VRGTwxC6z1zCCMB4680Qqyu2mxODMZRmx6lEi+sW/uF3W9EPKe6OHBCbK 5iwHFQdlz8rjnI2UFwCVBRMbUKvSeRfkFpXUafS0pEgcHAEjb+oxwQOmn W8/c1cJRwP5AxaHzAX1DrC0aRztMvNwBoH957J+NN8+MFWH754QZsPW0u FUavGSuGIzCJ9KfOLJNkEmggNfS9Lil6cSGlVDmmCL3YaTmTUlhooaHfw guYed94fKkPRYtug9ygtsl8FVsdoi79KxWrYWudAFkD81X9cUhu+pVssI w==; X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="372077465" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="372077465" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 01:54:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="793418404" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="793418404" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga001.jf.intel.com with ESMTP; 24 Oct 2023 01:54:02 -0700 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Yongwei Ma , Zhao Liu Subject: [PATCH v5 19/20] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Date: Tue, 24 Oct 2023 17:03:22 +0800 Message-Id: <20231024090323.1859210-20-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231024090323.1859210-1-zhao1.liu@linux.intel.com> References: <20231024090323.1859210-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Zhao Liu The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information for cpuid 0x8000001D") adds the cache topology for AMD CPU by encoding the number of sharing threads directly. From AMD's APM, NumSharingCache (CPUID[0x8000001D].EAX[bits 25:14]) means [1]: The number of logical processors sharing this cache is the value of this field incremented by 1. To determine which logical processors are sharing a cache, determine a Share Id for each processor as follows: ShareId = LocalApicId >> log2(NumSharingCache+1) Logical processors with the same ShareId then share a cache. If NumSharingCache+1 is not a power of two, round it up to the next power of two. From the description above, the calculation of this field should be same as CPUID[4].EAX[bits 25:14] for Intel CPUs. So also use the offsets of APIC ID to calculate this field. [1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology Information Signed-off-by: Zhao Liu Reviewed-by: Babu Moger Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin --- Changes since v3: * Rewrite the subject. (Babu) * Delete the original "comment/help" expression, as this behavior is confirmed for AMD CPUs. (Babu) * Rename "num_apic_ids" (v3) to "num_sharing_cache" to match spec definition. (Babu) Changes since v1: * Rename "l3_threads" to "num_apic_ids" in encode_cache_cpuid8000001d(). (Yanan) * Add the description of the original commit and add Cc. --- target/i386/cpu.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 90393396a0a4..226c5be6ea95 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -483,7 +483,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t l3_threads; + uint32_t num_sharing_cache; assert(cache->size == cache->line_size * cache->associativity * cache->partitions * cache->sets); @@ -492,13 +492,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, /* L3 is shared among multiple cores */ if (cache->level == 3) { - l3_threads = topo_info->modules_per_die * - topo_info->cores_per_module * - topo_info->threads_per_core; - *eax |= (l3_threads - 1) << 14; + num_sharing_cache = 1 << apicid_die_offset(topo_info); } else { - *eax |= ((topo_info->threads_per_core - 1) << 14); + num_sharing_cache = 1 << apicid_core_offset(topo_info); } + *eax |= (num_sharing_cache - 1) << 14; assert(cache->line_size > 0); assert(cache->partitions > 0);