From patchwork Tue Oct 24 09:03:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13434095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A5C9C25B47 for ; Tue, 24 Oct 2023 08:53:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234101AbjJXIxG (ORCPT ); Tue, 24 Oct 2023 04:53:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234055AbjJXIw7 (ORCPT ); Tue, 24 Oct 2023 04:52:59 -0400 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74FA01700 for ; Tue, 24 Oct 2023 01:52:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698137563; x=1729673563; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O4cakiDYK5PmInEf6axm43xrdaxTs7iFTrG/vVrudbU=; b=m6gF/tcnTt4MEBYSBFYtGX3qZmTkzC0YZLTWeUTVoaNoz+41/7Ipzdmc nka4boPcIKiMBvHdoUFwyugBMliYlQemj0sRG8F9LiL03OgsbDFDHXz/Q SbQmC0vUGRJovwILHRoW9EiPTTleDUkH01qeydzUMVDRjC/poIFzJpcdo K+7OfEIXo/NX0s4dfuUw2MP5F6mSYQwoaz2eEtvkw/00MDMCeTEj20aho HTLB9bzN5jskUqNMSc//kYjMpSad4BHoBIDJslWk9iAqdPsAg3p2uEci8 CjWjQthQ3AKbaDtozBtbHB0M+kB9aoAN06vlS30lz2e7n+7XVWVvvmnZI Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="5638382" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="5638382" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 01:52:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="793418060" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="793418060" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga001.jf.intel.com with ESMTP; 24 Oct 2023 01:52:37 -0700 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Yongwei Ma , Zhao Liu Subject: [PATCH v5 08/20] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Date: Tue, 24 Oct 2023 17:03:11 +0800 Message-Id: <20231024090323.1859210-9-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231024090323.1859210-1-zhao1.liu@linux.intel.com> References: <20231024090323.1859210-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Zhao Liu CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared by Intel and AMD CPUs. But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU (in CPUID[0x80000026]) have the different definitions with different enumeration values. Though CPUID[0x80000026] hasn't been implemented in QEMU, to avoid possible misunderstanding, split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] and introduce CPUID[0x1F]-specific topology types. Signed-off-by: Zhao Liu Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin --- Changes since v3: * New commit to prepare to refactor CPUID[0x1F] encoding. --- target/i386/cpu.c | 14 +++++++------- target/i386/cpu.h | 13 +++++++++---- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 46422cfb387c..ed65b7b8cf76 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6254,17 +6254,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, case 0: *eax = apicid_core_offset(&topo_info); *ebx = topo_info.threads_per_core; - *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; + *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; break; case 1: *eax = apicid_pkg_offset(&topo_info); *ebx = cpus_per_pkg; - *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; + *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; break; default: *eax = 0; *ebx = 0; - *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; + *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; } assert(!(*eax & ~0x1f)); @@ -6289,22 +6289,22 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, case 0: *eax = apicid_core_offset(&topo_info); *ebx = topo_info.threads_per_core; - *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; + *ecx |= CPUID_1F_ECX_TOPO_LEVEL_SMT << 8; break; case 1: *eax = apicid_die_offset(&topo_info); *ebx = topo_info.cores_per_die * topo_info.threads_per_core; - *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; + *ecx |= CPUID_1F_ECX_TOPO_LEVEL_CORE << 8; break; case 2: *eax = apicid_pkg_offset(&topo_info); *ebx = cpus_per_pkg; - *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; + *ecx |= CPUID_1F_ECX_TOPO_LEVEL_DIE << 8; break; default: *eax = 0; *ebx = 0; - *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; + *ecx |= CPUID_1F_ECX_TOPO_LEVEL_INVALID << 8; } assert(!(*eax & ~0x1f)); *ebx &= 0xffff; /* The count doesn't need to be reliable. */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a8f8fe3bbaf2..f6dff5f372bc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1009,10 +1009,15 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ /* CPUID[0xB].ECX level types */ -#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) -#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) -#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) -#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) +#define CPUID_B_ECX_TOPO_LEVEL_INVALID 0 +#define CPUID_B_ECX_TOPO_LEVEL_SMT 1 +#define CPUID_B_ECX_TOPO_LEVEL_CORE 2 + +/* COUID[0x1F].ECX level types */ +#define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID +#define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT +#define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE +#define CPUID_1F_ECX_TOPO_LEVEL_DIE 5 /* MSR Feature Bits */ #define MSR_ARCH_CAP_RDCL_NO (1U << 0)