From patchwork Fri Nov 17 07:50:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13458433 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ggGeGYzC" Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E079AD51 for ; Thu, 16 Nov 2023 23:39:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700206773; x=1731742773; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Vr2jcssLVuVjpC6rWPLuqvVV20V4lz6wIt3HNRawWDU=; b=ggGeGYzCNC68+Ii7s6jr59sMkMvDOaq+iYe4SQePQIJGzRuzDYhoVBWd s8FHQu6LhnnrAGKTshcv8MkQ+TFAIQsrX5TUEIW9pRMhq4NvB4FhzwiuG 1GXAQKSLQsMKCM+pUoF1tYZrOJ7DEBMlHw9BiE7XWrSbRcibHFqx8MJW9 2SqbgEe4GtK9f2mMud/8QNtOmlyh609tpotEprjy8YABEf/Px/gPSjwnN N6IHX/SUuSGbxGPqiI6UiD787hBe+fccavw7qLtjH0uGWM9d+WnjdpXwq 4oAiLTweOnZ5JNbhpizuroOzUScQmHqVuny1OkPQzQnIe9ySfpuoH7RHO Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10896"; a="395180285" X-IronPort-AV: E=Sophos;i="6.04,206,1695711600"; d="scan'208";a="395180285" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 23:39:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10896"; a="883042585" X-IronPort-AV: E=Sophos;i="6.04,206,1695711600"; d="scan'208";a="883042585" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmsmga002.fm.intel.com with ESMTP; 16 Nov 2023 23:39:28 -0800 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Babu Moger , Yongwei Ma , Zhao Liu , Robert Hoo Subject: [PATCH v6 02/16] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4] Date: Fri, 17 Nov 2023 15:50:52 +0800 Message-Id: <20231117075106.432499-3-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231117075106.432499-1-zhao1.liu@linux.intel.com> References: <20231117075106.432499-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the nearest power-of-2 integer. The nearest power-of-2 integer can be calculated by pow2ceil() or by using APIC ID offset (like L3 topology using 1 << die_offset [3]). But in fact, CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] are associated with APIC ID. For example, in linux kernel, the field "num_threads_sharing" (Bits 25 - 14) is parsed with APIC ID. And for another example, on Alder Lake P, the CPUID.04H:EAX[bits 31:26] is not matched with actual core numbers and it's calculated by: "(1 << (pkg_offset - core_offset)) - 1". Therefore the offset of APIC ID should be preferred to calculate nearest power-of-2 integer for CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26]: 1. d/i cache is shared in a core, 1 << core_offset should be used instand of "cs->nr_threads" in encode_cache_cpuid4() for CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]. 2. L2 cache is supposed to be shared in a core as for now, thereby 1 << core_offset should also be used instand of "cs->nr_threads" in encode_cache_cpuid4() for CPUID.04H.02H:EAX[bits 25:14]. 3. Similarly, the value for CPUID.04H:EAX[bits 31:26] should also be calculated with the bit width between the Package and SMT levels in the APIC ID (1 << (pkg_offset - core_offset) - 1). In addition, use APIC ID offset to replace "pow2ceil()" for cache_info_passthrough case. [1]: efb3934adf9e ("x86: cpu: make sure number of addressable IDs for processor cores meets the spec") [2]: d7caf13b5fcf ("x86: cpu: fixup number of addressable IDs for logical processors sharing cache") [3]: d65af288a84d ("i386: Update new x86_apicid parsing rules with die_offset support") Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistently") Suggested-by: Robert Hoo Signed-off-by: Zhao Liu Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin --- Changes since v3: * Fix compile warnings. (Babu) * Fix spelling typo. Changes since v1: * Use APIC ID offset to replace "pow2ceil()" for cache_info_passthrough case. (Yanan) * Split the L1 cache fix into a separate patch. * Rename the title of this patch (the original is "i386/cpu: Fix number of addressable IDs in CPUID.04H"). --- target/i386/cpu.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4a3621cc995a..069f0b1f19a0 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6013,7 +6013,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, { X86CPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); - uint32_t die_offset; uint32_t limit; uint32_t signature[3]; X86CPUTopoInfo topo_info; @@ -6097,39 +6096,56 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); int vcpus_per_socket = cs->nr_cores * cs->nr_threads; if (cs->nr_cores > 1) { + int addressable_cores_offset = + apicid_pkg_offset(&topo_info) - + apicid_core_offset(&topo_info); + *eax &= ~0xFC000000; - *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; + *eax |= (1 << (addressable_cores_offset - 1)) << 26; } if (host_vcpus_per_cache > vcpus_per_socket) { + int pkg_offset = apicid_pkg_offset(&topo_info); + *eax &= ~0x3FFC000; - *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; + *eax |= (1 << (pkg_offset - 1)) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { *eax = *ebx = *ecx = *edx = 0; } else { *eax = 0; + int addressable_cores_offset = apicid_pkg_offset(&topo_info) - + apicid_core_offset(&topo_info); + int core_offset, die_offset; + switch (count) { case 0: /* L1 dcache info */ + core_offset = apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - cs->nr_threads, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ + core_offset = apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - cs->nr_threads, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ + core_offset = apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - cs->nr_threads, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ die_offset = apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << die_offset), cs->nr_cores, + (1 << die_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; }