From patchwork Thu Nov 30 14:41:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13474508 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nd87b+Co" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BF7B93 for ; Thu, 30 Nov 2023 06:33:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701354784; x=1732890784; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/4XB1+0XSfZXJW6ggYvVG8+UQ24RT1LIudOfD5YSaJw=; b=nd87b+ConG9yKkEy3y3r0pIAQ6enQIYkVPbicZH7YjpCDWLHnWIsg8Yf 8Ati+jYYFU/X4ZI7UM2Mv1ZG5V1j6Z2fptjTzXfFhoUZTGwEya8DRCFxX kSm9K2QTy6qlnLipNkDesV4C/8AMGLTNQdbWZg74yVc9sZpwdVAz+Empz BH0kf2Z1SfWiBlYCoCcapTCuyAmxlPwsqKTjYQhQ/iymgbWu1qGONdJ9w hV9us2ZY8QWqOFaI7Q+6Qq1XsT/pCjJkurOLdec6RAS/TcfphvjjuMZAi kKweD4tembUSJuAzTzdskxG07A0UxHfd5xA+OzSgLUBsAbRPZbVY9ajaW A==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="479531856" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="479531856" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 06:33:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="942729971" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="942729971" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga005.jf.intel.com with ESMTP; 30 Nov 2023 06:32:54 -0800 From: Zhao Liu To: Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Richard Henderson , "Michael S . Tsirkin" , Jason Wang , Nicholas Piggin , Daniel Henrique Barboza , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?b?RnLDqWTDqXJp?= =?utf-8?b?YyBCYXJyYXQ=?= , David Gibson , Harsh Prateek Bora , Stefano Stabellini , Anthony Perard , Paul Durrant , Gerd Hoffmann , Peter Maydell , Alistair Francis , "Edgar E . Iglesias" , =?utf-8?q?Daniel_P_=2E_Ber?= =?utf-8?q?rang=C3=A9?= , Bin Meng , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, xen-devel@lists.xenproject.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: Nina Schoetterl-Glausch , Thomas Huth , Zhiyuan Lv , Zhenyu Wang , Yongwei Ma , Zhao Liu Subject: [RFC 16/41] PPC/ppc-core: Limit plugged-threads and nr-threads to be equal Date: Thu, 30 Nov 2023 22:41:38 +0800 Message-Id: <20231130144203.2307629-17-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> References: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu PPC supports CPU hotplug at core granularity, thus ppc-core only accepts all CPUs in a core are plugged. Check if plugged_threads and nr_threads are equal when ppc-core realizes. Signed-off-by: Zhao Liu --- hw/ppc/ppc_core.c | 18 ++++++++++++++++++ include/hw/ppc/ppc_core.h | 1 + 2 files changed, 19 insertions(+) diff --git a/hw/ppc/ppc_core.c b/hw/ppc/ppc_core.c index 4433b54af506..3857f3150052 100644 --- a/hw/ppc/ppc_core.c +++ b/hw/ppc/ppc_core.c @@ -53,20 +53,38 @@ static void powerpc_core_prop_set_core_id(Object *obj, Visitor *v, core->core_id = value; } +static void powerpc_core_realize(DeviceState *dev, Error **errp) +{ + CPUCore *core = CPU_CORE(dev); + PowerPCCoreClass *ppc_class = POWERPC_CORE_GET_CLASS(dev); + + if (core->plugged_threads != -1 && + core->nr_threads != core->plugged_threads) { + error_setg(errp, "nr_threads and plugged-threads must be equal"); + return; + } + + ppc_class->parent_realize(dev, errp); +} + static void powerpc_core_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCoreClass *ppc_class = POWERPC_CORE_CLASS(oc); object_class_property_add(oc, "core-id", "int", powerpc_core_prop_get_core_id, powerpc_core_prop_set_core_id, NULL, NULL); + device_class_set_parent_realize(dc, powerpc_core_realize, + &ppc_class->parent_realize); } static const TypeInfo powerpc_core_type_info = { .name = TYPE_POWERPC_CORE, .parent = TYPE_CPU_CORE, .abstract = true, + .class_size = sizeof(PowerPCCoreClass), .class_init = powerpc_core_class_init, .instance_size = sizeof(PowerPCCore), }; diff --git a/include/hw/ppc/ppc_core.h b/include/hw/ppc/ppc_core.h index bcc83e426e3f..1207d220872a 100644 --- a/include/hw/ppc/ppc_core.h +++ b/include/hw/ppc/ppc_core.h @@ -34,6 +34,7 @@ struct PowerPCCoreClass { CPUCoreClass parent_class; /*< public >*/ + DeviceRealize parent_realize; }; struct PowerPCCore {