From patchwork Thu Nov 30 14:41:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13474512 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jzyv9MiK" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D2B1196 for ; Thu, 30 Nov 2023 06:33:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701354822; x=1732890822; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tVF0CmmcOBEuYyYp6LOjwJOc13qp/jolnKC9SQQ9zpo=; b=jzyv9MiKM/URV9xC1BdYmNNmniC8FELDE+7e9rruAsu7WLwOoPudgvhf bTewpqWOWfRX8wdCrw0QHf0JR63ucYB1H3z6wjCgVHwqlFVvQPkolv6ks GGNxVi1RzONLf3xDdjNTS7tlf8x5cca7avIB4khiCZqwwF6BJ/9AdhrZD haNC8E7xmr8F1Ob4T8y++uoPEnrdgFd6glwBnAc0Mv+ux1ZsZAc8sRLdq SJLNDViXT6W5pyKqGnmt6nF7gyPmffPjHMDI8ZdIqEqDBekqFq4J2jzz5 R15YIKzrunhQv45TMA4aUcE+B6OOSgYJJm5bjrdkwc+iDYNY+7UC/MlAg A==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="479532006" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="479532006" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 06:33:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="942730040" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="942730040" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga005.jf.intel.com with ESMTP; 30 Nov 2023 06:33:32 -0800 From: Zhao Liu To: Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Richard Henderson , "Michael S . Tsirkin" , Jason Wang , Nicholas Piggin , Daniel Henrique Barboza , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?b?RnLDqWTDqXJp?= =?utf-8?b?YyBCYXJyYXQ=?= , David Gibson , Harsh Prateek Bora , Stefano Stabellini , Anthony Perard , Paul Durrant , Gerd Hoffmann , Peter Maydell , Alistair Francis , "Edgar E . Iglesias" , =?utf-8?q?Daniel_P_=2E_Ber?= =?utf-8?q?rang=C3=A9?= , Bin Meng , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, xen-devel@lists.xenproject.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: Nina Schoetterl-Glausch , Thomas Huth , Zhiyuan Lv , Zhenyu Wang , Yongwei Ma , Zhao Liu Subject: [RFC 20/41] hw/cpu/cluster: Descript cluster is not only used for TCG in comment Date: Thu, 30 Nov 2023 22:41:42 +0800 Message-Id: <20231130144203.2307629-21-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> References: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu Update the comment to make the cpu-cluster description more general for both TCG and accel cases. Signed-off-by: Zhao Liu --- hw/cpu/cluster.c | 2 +- include/hw/cpu/cluster.h | 20 +++++++++++++++----- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index 340cfad9f8f1..27ab9e25a265 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -1,5 +1,5 @@ /* - * QEMU CPU cluster + * CPU cluster abstract device * * Copyright (c) 2018 GreenSocs SAS * diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h index c038f05ddc9f..b3185e2f2566 100644 --- a/include/hw/cpu/cluster.h +++ b/include/hw/cpu/cluster.h @@ -1,5 +1,5 @@ /* - * QEMU CPU cluster + * CPU cluster abstract device * * Copyright (c) 2018 GreenSocs SAS * @@ -24,17 +24,27 @@ #include "qom/object.h" /* - * CPU Cluster type + * # CPU Cluster * - * A cluster is a group of CPUs which are all identical and have the same view - * of the rest of the system. It is mainly an internal QEMU representation and - * does not necessarily match with the notion of clusters on the real hardware. + * A cluster is a group of CPUs, that is, a level above the CPU (or Core). + * + * - For accel case, it's a CPU topology level concept above cores, in which + * the cores may share some resources (L2 cache or some others like L3 + * cache tags, depending on the Archs). It is used to emulate the physical + * CPU cluster/module. + * + * - For TCG, cluster is used to organize CPUs directly without core. In one + * cluster, CPUs are all identical and have the same view of the rest of the + * system. It is mainly an internal QEMU representation and may not necessarily + * match with the notion of clusters on the real hardware. * * If CPUs are not identical (for example, Cortex-A53 and Cortex-A57 CPUs in an * Arm big.LITTLE system) they should be in different clusters. If the CPUs do * not have the same view of memory (for example the main CPU and a management * controller processor) they should be in different clusters. * + * # Use case for cluster in TCG + * * A cluster is created by creating an object of TYPE_CPU_CLUSTER, and then * adding the CPUs to it as QOM child objects (e.g. using the * object_initialize_child() or object_property_add_child() functions).