From patchwork Thu Nov 30 14:41:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13474520 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IbywlgGW" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 190CDBD for ; Thu, 30 Nov 2023 06:34:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701354897; x=1732890897; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FbB6vbX6bR4dqU1fCV07ghJ+c5nYYHlqh35CAqrTsmY=; b=IbywlgGWwzmRSkieJZJZXlyD9H4oQQrZoiKliEEBDq0wrIyM+KDJIpwm tOZ0qE0wH1gidTozB2foJF7pizA278GWOb25H0hIzZAAlYjsDA1ElZjyb YvI8r/qYJdTHTvswt6CZbV2nJtCXCs7zJy2K40kI9WJ/eMKnb3Qv6lY+6 A9RLYi4O7YrPWy6FhR54JoITebl602V0tVxZbcB3dkq5pQ8tcAWhQmtei XLDnCw3RVMT3ssC97dpUDUU4nEDQTzfodQl+2o/NU6lVasqq4SIL9091k utLijhs+VvJWXgqP/5LqKkpg2jR9KQ756xoFfq4ZZXnPLpB28nEk+uPVO w==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="479532314" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="479532314" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 06:34:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="942730130" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="942730130" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga005.jf.intel.com with ESMTP; 30 Nov 2023 06:34:47 -0800 From: Zhao Liu To: Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Richard Henderson , "Michael S . Tsirkin" , Jason Wang , Nicholas Piggin , Daniel Henrique Barboza , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?b?RnLDqWTDqXJp?= =?utf-8?b?YyBCYXJyYXQ=?= , David Gibson , Harsh Prateek Bora , Stefano Stabellini , Anthony Perard , Paul Durrant , Gerd Hoffmann , Peter Maydell , Alistair Francis , "Edgar E . Iglesias" , =?utf-8?q?Daniel_P_=2E_Ber?= =?utf-8?q?rang=C3=A9?= , Bin Meng , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, xen-devel@lists.xenproject.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: Nina Schoetterl-Glausch , Thomas Huth , Zhiyuan Lv , Zhenyu Wang , Yongwei Ma , Zhao Liu Subject: [RFC 28/41] hw/core/slot: Maintain the core queue in CPU slot Date: Thu, 30 Nov 2023 22:41:50 +0800 Message-Id: <20231130144203.2307629-29-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> References: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu Maintain the cores queue at cpu-slot to facilitate direct traversal of all cores. Signed-off-by: Zhao Liu --- hw/core/cpu-slot.c | 43 ++++++++++++++++++++++++++++++++++++++ include/hw/core/cpu-slot.h | 9 ++++++++ include/hw/cpu/core.h | 2 ++ 3 files changed, 54 insertions(+) diff --git a/hw/core/cpu-slot.c b/hw/core/cpu-slot.c index 5aef5b0189c2..a6b7d98dea18 100644 --- a/hw/core/cpu-slot.c +++ b/hw/core/cpu-slot.c @@ -22,6 +22,40 @@ #include "hw/core/cpu-slot.h" +static void cpu_slot_add_topo_info(CPUTopoState *root, CPUTopoState *child) +{ + CPUSlot *slot = CPU_SLOT(root); + CPUTopoLevel level = CPU_TOPO_LEVEL(child); + + if (level == CPU_TOPO_CORE) { + QTAILQ_INSERT_TAIL(&slot->cores, CPU_CORE(child), node); + } + return; +} + +static void cpu_slot_del_topo_info(CPUTopoState *root, CPUTopoState *child) +{ + CPUSlot *slot = CPU_SLOT(root); + CPUTopoLevel level = CPU_TOPO_LEVEL(child); + + if (level == CPU_TOPO_CORE) { + QTAILQ_REMOVE(&slot->cores, CPU_CORE(child), node); + } + return; +} + +static void cpu_slot_update_topo_info(CPUTopoState *root, CPUTopoState *child, + bool is_realize) +{ + g_assert(child->parent); + + if (is_realize) { + cpu_slot_add_topo_info(root, child); + } else { + cpu_slot_del_topo_info(root, child); + } +} + static void cpu_slot_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -31,12 +65,21 @@ static void cpu_slot_class_init(ObjectClass *oc, void *data) dc->user_creatable = false; tc->level = CPU_TOPO_ROOT; + tc->update_topo_info = cpu_slot_update_topo_info; +} + +static void cpu_slot_instance_init(Object *obj) +{ + CPUSlot *slot = CPU_SLOT(obj); + + QTAILQ_INIT(&slot->cores); } static const TypeInfo cpu_slot_type_info = { .name = TYPE_CPU_SLOT, .parent = TYPE_CPU_TOPO, .class_init = cpu_slot_class_init, + .instance_init = cpu_slot_instance_init, .instance_size = sizeof(CPUSlot), }; diff --git a/include/hw/core/cpu-slot.h b/include/hw/core/cpu-slot.h index 718c8ecaa751..d2a1160562be 100644 --- a/include/hw/core/cpu-slot.h +++ b/include/hw/core/cpu-slot.h @@ -22,17 +22,26 @@ #define CPU_SLOT_H #include "hw/core/cpu-topo.h" +#include "hw/cpu/core.h" #include "hw/qdev-core.h" #define TYPE_CPU_SLOT "cpu-slot" OBJECT_DECLARE_SIMPLE_TYPE(CPUSlot, CPU_SLOT) +/** + * CPUSlot: + * @cores: Queue consisting of all the cores in the topology tree + * where the cpu-slot is the root. cpu-slot can maintain similar + * queues for other topology levels to facilitate traversal + * when necessary. + */ struct CPUSlot { /*< private >*/ CPUTopoState parent_obj; /*< public >*/ + QTAILQ_HEAD(, CPUCore) cores; }; #endif /* CPU_SLOT_H */ diff --git a/include/hw/cpu/core.h b/include/hw/cpu/core.h index 591240861efb..65dc10931190 100644 --- a/include/hw/cpu/core.h +++ b/include/hw/cpu/core.h @@ -40,6 +40,8 @@ struct CPUCore { * "-device"/"device_add"? */ int plugged_threads; + + QTAILQ_ENTRY(CPUCore) node; }; #endif