[v1,02/10] RISC-V: Add FIRMWARE_READ_HI definition

Message ID	20231218104107.2976925-3-atishp@rivosinc.com (mailing list archive)
State	New, archived
Headers	show Received: from mail-oo1-f51.google.com (mail-oo1-f51.google.com [209.85.161.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16E861798C for <kvm@vger.kernel.org>; Mon, 18 Dec 2023 10:41:20 +0000 (UTC) From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Anup Patel <anup@brainfault.org>, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, Icenowy Zheng <uwu@icenowy.me>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Will Deacon <will@kernel.org> Subject: [v1 02/10] RISC-V: Add FIRMWARE_READ_HI definition Date: Mon, 18 Dec 2023 02:40:59 -0800 Message-Id: <20231218104107.2976925-3-atishp@rivosinc.com> In-Reply-To: <20231218104107.2976925-1-atishp@rivosinc.com> References: <20231218104107.2976925-1-atishp@rivosinc.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest \| expand [v1,00/10] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest [v1,01/10] RISC-V: Fix the typo in Scountovf CSR name [v1,02/10] RISC-V: Add FIRMWARE_READ_HI definition [v1,03/10] drivers/perf: riscv: Read upper bits of a firmware counter [v1,04/10] RISC-V: Add SBI PMU snapshot definitions [v1,05/10] drivers/perf: riscv: Implement SBI PMU snapshot function [v1,06/10] RISC-V: KVM: No need to update the counter value during reset [v1,07/10] RISC-V: KVM: No need to exit to the user space if perf event failed [v1,08/10] RISC-V: KVM: Implement SBI PMU Snapshot feature [v1,09/10] RISC-V: KVM: Add perf sampling support for guests [v1,10/10] RISC-V: KVM: Support 64 bit firmware counters on RV32

Message ID

20231218104107.2976925-3-atishp@rivosinc.com (mailing list archive)

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New, archived

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From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Anup Patel <anup@brainfault.org>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alexghiti@rivosinc.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Atish Patra <atishp@atishpatra.org>,
	Guo Ren <guoren@kernel.org>,
	Icenowy Zheng <uwu@icenowy.me>,
	kvm-riscv@lists.infradead.org,
	kvm@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Mark Rutland <mark.rutland@arm.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Will Deacon <will@kernel.org>
Subject: [v1 02/10] RISC-V: Add FIRMWARE_READ_HI definition
Date: Mon, 18 Dec 2023 02:40:59 -0800
Message-Id: <20231218104107.2976925-3-atishp@rivosinc.com>
In-Reply-To: <20231218104107.2976925-1-atishp@rivosinc.com>
References: <20231218104107.2976925-1-atishp@rivosinc.com>
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Series

RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest | expand

Commit Message

Atish Kumar Patra Dec. 18, 2023, 10:40 a.m. UTC

SBI v2.0 added another function to SBI PMU extension to read
the upper bits of a counter with width larger than XLEN.

Add the definition for that function.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/include/asm/sbi.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 0892f4421bc4..f3eeca79a02d 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -121,6 +121,7 @@  enum sbi_ext_pmu_fid {
 	SBI_EXT_PMU_COUNTER_START,
 	SBI_EXT_PMU_COUNTER_STOP,
 	SBI_EXT_PMU_COUNTER_FW_READ,
+	SBI_EXT_PMU_COUNTER_FW_READ_HI,
 };
 
 union sbi_pmu_ctr_info {

[v1,02/10] RISC-V: Add FIRMWARE_READ_HI definition

Commit Message

Patch