From patchwork Mon Dec 18 10:40:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13496542 Received: from mail-oo1-f51.google.com (mail-oo1-f51.google.com [209.85.161.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16E861798C for ; Mon, 18 Dec 2023 10:41:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Pf1OvCGw" Received: by mail-oo1-f51.google.com with SMTP id 006d021491bc7-5906df1d2adso1112403eaf.2 for ; Mon, 18 Dec 2023 02:41:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1702896080; x=1703500880; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=892a7MXGmC/bLYrq2xxQmZbI6vgYpLZafzDkJ/FX6g8=; b=Pf1OvCGwJ8z8lh9BXygrDkqJiDparXSzZzQsOlM2jSpRqpAPfI8+Wt3Z0Pf2Jj9eXW S2DbY4OLMJH13S52qglLqzaUTYyWwliq4I3ChoyxL2uXNX8kAfjlha5+jAUh8lrHy8h7 OXPGK8EIwjSSf7Nd6tRIrrcVwQkWvj0DttIoH7E3qSYJsQUlTtriu4POqixXiQeN+x5h WJNUmRArDXll2SAuZnENR00jNuOh4T1vnPSlmygwLaBuV/94wousBgzXJirJpkDyHUKS 5bHvRvhzfyM9NgUqoVjF7qcRODEUP9aegSDnjU1frURC6ErxdFmPBTekqxeo3K6Zfj2i IXyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702896080; x=1703500880; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=892a7MXGmC/bLYrq2xxQmZbI6vgYpLZafzDkJ/FX6g8=; b=NNGo5DIBeTKOXaP5Qut1r4tyxIgzQfV2ypgvt2In/oFTsxPwx0CFtXkkCKFJUgBxqR YpC+65p4D5o7jC5CP8QXSMDI+VyFd8V9HseHMjiV0D8/k0TQ/5BnJOk2ZjQswprqEVOl AtqTGuzBAAq0r7vy+89Ipksk78d+SfdfBs97B/2mNtFsBIisesfKg3cwXIhcbXOzHj7P yvgl/NDzdxZVZIw76l5hdDKEWVoq72BJ7nazbYEFPrepRtz5P+m2QI2Koz5dobJbyJJ7 0u0SVncudVTMO1GpphAEESSHK2ChRW/S87jgsmKxk+1tpw2LMfgag0FBFJlO4VbMURQk qA/A== X-Gm-Message-State: AOJu0YzYuVJQ6Dci8BomKkIm1h5cA7qPL7yPE4t0HehEK6T8vaXRg0oL RxfSZJIRngy5O7VlNgCmmwSSZA== X-Google-Smtp-Source: AGHT+IFgByVnLmmTZ/wPh8GAxGl3YQsD3+CdxKG6a7sBAikC48zmomkZqc6rzvayrv+U3EDDZxFKJQ== X-Received: by 2002:a05:6820:162c:b0:590:5c02:a4d2 with SMTP id bb44-20020a056820162c00b005905c02a4d2mr8417153oob.13.1702896080113; Mon, 18 Dec 2023 02:41:20 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 185-20020a4a1ac2000000b005907ad9f302sm574970oof.37.2023.12.18.02.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 02:41:19 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Conor Dooley , Anup Patel , Albert Ou , Alexandre Ghiti , Andrew Jones , Atish Patra , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Will Deacon Subject: [v1 02/10] RISC-V: Add FIRMWARE_READ_HI definition Date: Mon, 18 Dec 2023 02:40:59 -0800 Message-Id: <20231218104107.2976925-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218104107.2976925-1-atishp@rivosinc.com> References: <20231218104107.2976925-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 SBI v2.0 added another function to SBI PMU extension to read the upper bits of a counter with width larger than XLEN. Add the definition for that function. Acked-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 0892f4421bc4..f3eeca79a02d 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -121,6 +121,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_START, SBI_EXT_PMU_COUNTER_STOP, SBI_EXT_PMU_COUNTER_FW_READ, + SBI_EXT_PMU_COUNTER_FW_READ_HI, }; union sbi_pmu_ctr_info {