| Message ID | 20231225151203.152687-2-dtatulea@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show
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Tsirkin" <mst@redhat.com>, Jason Wang <jasowang@redhat.com>, Eugenio Perez Martin <eperezma@redhat.com>, Si-Wei Liu <si-wei.liu@oracle.com>, Saeed Mahameed <saeedm@nvidia.com>, Leon Romanovsky <leon@kernel.org>, <virtualization@lists.linux-foundation.org>, Gal Pressman <gal@nvidia.com> CC: Dragos Tatulea <dtatulea@nvidia.com>, <kvm@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Parav Pandit <parav@nvidia.com>, Xuan Zhuo <xuanzhuo@linux.alibaba.com> Subject: [PATCH mlx5-vhost v5 1/8] vdpa/mlx5: Expose resumable vq capability Date: Mon, 25 Dec 2023 17:11:56 +0200 Message-ID: <20231225151203.152687-2-dtatulea@nvidia.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231225151203.152687-1-dtatulea@nvidia.com> References: <20231225151203.152687-1-dtatulea@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: <kvm.vger.kernel.org> List-Subscribe: <mailto:kvm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:kvm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A108:EE_|CYYPR12MB8653:EE_ X-MS-Office365-Filtering-Correlation-Id: 8a3384b6-ae4e-4336-130a-08dc055be434 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lYxNVcwBxJeeLDR+aUjeO9D9vkngNoz8u7S2bVxnYc8uTNlkA+FVt1+tup/F/PAAtB2GnxZnxQFTWeUIGRFiWNPRM0hkOVQtUOVY765TRpPW6vMd+iCDV6M94XUJCVwNJK2EeduBn+k2O6Aw7kwJIO2OPsUeK2NRHSIXDIej4xjVIIgutuso2jv20wHsYIck1DelhZxNZ34Xv30XyJMmNuQ4IR6eBG7JCOuyJsmGXzY3krDXamwePBNry3hTXsPJWfltwFzyXcK2gLXrzl5z58BYqMSt104EVc2+Fh/DgMeJOYyszMxbBuAadLjwHfOIcuqzvXV7T6S2R4+EOjUapuxer8BoFD2q8BQjAYIfMYXiI+hONfz3meTbayaYgjdlyjECuQWnx+GJdoza6AuZAFSkeyJTovKOHnFGDEeB8CchXKcrAQow4bhsltFGlCP+7YAvYok1V4QQF9rvqTibjDih1DOiCw10pam5AsI74REojd24Mg7oSeY6+OkzPMxbkNIPSw4U35bSE2D25TIx58PzHXZjbySV395zojUWmjsPwr/H2UigKUwR55DZmSWPvdlb+4ExZr+5goRikaZFNyE9qJ2NHqYx7RTfY2RFY9ZLkgT+jw+OwjUr60+6Ik8DhQZUwj0iyHkM3gd2QMgBhy3uB62W8eVIQJQAYZFrScdX7IZN5TtS0xa/4mI49FiQbaBlD8Qf/VJGYBJrYQvI6xjTfWbVb+ZxZEAScJ2t/EMFVjV87QqCbKBn7pNZSqq2 X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(346002)(39860400002)(136003)(230922051799003)(82310400011)(451199024)(1800799012)(186009)(64100799003)(40470700004)(46966006)(36840700001)(40480700001)(66574015)(2616005)(26005)(426003)(336012)(1076003)(40460700003)(86362001)(36756003)(7636003)(82740400003)(356005)(47076005)(83380400001)(8676002)(4326008)(5660300002)(6666004)(36860700001)(110136005)(478600001)(54906003)(6636002)(70586007)(316002)(70206006)(41300700001)(2906002)(4744005)(8936002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Dec 2023 15:12:20.6517 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a3384b6-ae4e-4336-130a-08dc055be434 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A108.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8653 |
| Series |
vdpa/mlx5: Add support for resumable vqs
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expand
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diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 6f3631425f38..9eaceaf6bcb0 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1236,7 +1236,8 @@ struct mlx5_ifc_virtio_emulation_cap_bits { u8 reserved_at_c0[0x13]; u8 desc_group_mkey_supported[0x1]; - u8 reserved_at_d4[0xc]; + u8 freeze_to_rdy_supported[0x1]; + u8 reserved_at_d5[0xb]; u8 reserved_at_e0[0x20];