From patchwork Thu Jan 11 08:56:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13516977 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E2BD15E9B; Thu, 11 Jan 2024 08:56:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DP8agTYy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704963398; x=1736499398; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=SvyQgb7E1GjbbhEZauDFduuMMCCNLr60ulcJzDeIqyo=; b=DP8agTYy0b5+FhTki9djPAUS+/vamp2KB8DIxtDRqMpktfXwTKgzbxeh ol2Q9CHdXn8+W9rnIfU7+0Hm8WxgpPhjG3FgbqudzDGO5m1gTJX8Nvlfd S3TBATBzVImTM9KmdEE4TABSLI3bul4DoE5G560+sX+yNAMs96mRsI2TV /iiW8QiV7V8z/g+8+Bzj94m8nzEO7xEoOck3flZWJ3xuHr1I1m6K+XmBc cx5Jv10HfQVrhwrGIn6mJgKtneMC/P511tyj/rCYlyCEY/mrchADfh18o 1nq6Nd7GHb1NLsygLgLOJUPq6uoLRlrNsgkmki0/STpT6gcteg6UPeAPk w==; X-IronPort-AV: E=McAfee;i="6600,9927,10949"; a="6144925" X-IronPort-AV: E=Sophos;i="6.04,185,1695711600"; d="scan'208";a="6144925" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2024 00:56:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10949"; a="905877668" X-IronPort-AV: E=Sophos;i="6.04,185,1695711600"; d="scan'208";a="905877668" Received: from ericwong-mobl2.amr.corp.intel.com (HELO desk) ([10.209.43.169]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2024 00:56:36 -0800 Date: Thu, 11 Jan 2024 00:56:36 -0800 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Peter Zijlstra , Josh Poimboeuf , Andy Lutomirski , Jonathan Corbet , Sean Christopherson , Paolo Bonzini , tony.luck@intel.com, ak@linux.intel.com, tim.c.chen@linux.intel.com, Andrew Cooper , Nikolay Borisov Cc: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, Alyssa Milburn , Daniel Sneddon , antonio.gomez.iglesias@linux.intel.com, Pawan Gupta Subject: [PATCH v5 3/6] x86/entry_32: Add VERW just before userspace transition Message-ID: <20240111-delay-verw-v5-3-a3b234933ea6@linux.intel.com> X-Mailer: b4 0.12.3 References: <20240111-delay-verw-v5-0-a3b234933ea6@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240111-delay-verw-v5-0-a3b234933ea6@linux.intel.com> As done for entry_64, add support for executing VERW late in exit to user path for 32-bit mode. Signed-off-by: Pawan Gupta --- arch/x86/entry/entry_32.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S index c73047bf9f4b..fba427646805 100644 --- a/arch/x86/entry/entry_32.S +++ b/arch/x86/entry/entry_32.S @@ -885,6 +885,7 @@ SYM_FUNC_START(entry_SYSENTER_32) BUG_IF_WRONG_CR3 no_user_check=1 popfl popl %eax + CLEAR_CPU_BUFFERS /* * Return back to the vDSO, which will pop ecx and edx. @@ -954,6 +955,7 @@ restore_all_switch_stack: /* Restore user state */ RESTORE_REGS pop=4 # skip orig_eax/error_code + CLEAR_CPU_BUFFERS .Lirq_return: /* * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization @@ -1146,6 +1148,7 @@ SYM_CODE_START(asm_exc_nmi) /* Not on SYSENTER stack. */ call exc_nmi + CLEAR_CPU_BUFFERS jmp .Lnmi_return .Lnmi_from_sysenter_stack: