diff mbox series

[kvm-unit-tests,v2,23/24] gitlab-ci: Add riscv64 tests

Message ID	20240126142324.66674-49-andrew.jones@linux.dev (mailing list archive)
State	New, archived
Headers	show Received: from out-189.mta0.migadu.com (out-189.mta0.migadu.com [91.218.175.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 528F81F955 for <kvm@vger.kernel.org>; Fri, 26 Jan 2024 14:24:31 +0000 (UTC) From: Andrew Jones <andrew.jones@linux.dev> To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, kvmarm@lists.linux.dev Cc: ajones@ventanamicro.com, anup@brainfault.org, atishp@atishpatra.org, pbonzini@redhat.com, thuth@redhat.com, alexandru.elisei@arm.com, eric.auger@redhat.com Subject: [kvm-unit-tests PATCH v2 23/24] gitlab-ci: Add riscv64 tests Date: Fri, 26 Jan 2024 15:23:48 +0100 Message-ID: <20240126142324.66674-49-andrew.jones@linux.dev> In-Reply-To: <20240126142324.66674-26-andrew.jones@linux.dev> References: <20240126142324.66674-26-andrew.jones@linux.dev> Precedence: bulk MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit
Series	Introduce RISC-V \| expand [kvm-unit-tests,v2,00/24] Introduce RISC-V [kvm-unit-tests,v2,01/24] configure: Add ARCH_LIBDIR [kvm-unit-tests,v2,02/24] riscv: Initial port, hello world [kvm-unit-tests,v2,03/24] arm/arm64: Move cpumask.h to common lib [kvm-unit-tests,v2,04/24] arm/arm64: Share cpu online, present and idle masks [kvm-unit-tests,v2,05/24] riscv: Add DT parsing [kvm-unit-tests,v2,06/24] riscv: Add initial SBI support [kvm-unit-tests,v2,07/24] riscv: Add run script and unittests.cfg [kvm-unit-tests,v2,08/24] riscv: Add riscv32 support [kvm-unit-tests,v2,09/24] riscv: Add exception handling [kvm-unit-tests,v2,10/24] riscv: Add backtrace support [kvm-unit-tests,v2,11/24] arm/arm64: Generalize wfe/sev names in smp.c [kvm-unit-tests,v2,12/24] arm/arm64: Remove spinlocks from on_cpu_async [kvm-unit-tests,v2,13/24] arm/arm64: Share on_cpus [kvm-unit-tests,v2,14/24] riscv: Compile with march [kvm-unit-tests,v2,15/24] riscv: Add SMP support [kvm-unit-tests,v2,16/24] arm/arm64: Share memregions [kvm-unit-tests,v2,17/24] riscv: Populate memregions and switch to page allocator [kvm-unit-tests,v2,18/24] riscv: Add MMU support [kvm-unit-tests,v2,19/24] riscv: Enable the MMU in secondaries [kvm-unit-tests,v2,20/24] riscv: Enable vmalloc [kvm-unit-tests,v2,21/24] lib: Add strcasecmp and strncasecmp [kvm-unit-tests,v2,22/24] riscv: Add isa string parsing [kvm-unit-tests,v2,23/24] gitlab-ci: Add riscv64 tests [kvm-unit-tests,v2,24/24] MAINTAINERS: Add riscv

Commit Message

Andrew Jones Jan. 26, 2024, 2:23 p.m. UTC

Add build/run tests for riscv64. We would also add riscv32, but Fedora
doesn't package what we need for that.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>
---
 .gitlab-ci.yml | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff mbox series

Patch

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 273ec9a7224b..71d986e9884e 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -87,6 +87,23 @@  build-ppc64le:
      | tee results.txt
  - if grep -q FAIL results.txt ; then exit 1 ; fi
 
+# build-riscv32:
+# Fedora doesn't package a riscv32 compiler for QEMU. Oh, well.
+
+# Select 'rv64' with PROCESSOR_OVERRIDE in case QEMU is too old to have 'max'
+build-riscv64:
+ extends: .intree_template
+ script:
+ - dnf install -y qemu-system-riscv gcc-riscv64-linux-gnu
+ - ./configure --arch=riscv64 --cross-prefix=riscv64-linux-gnu-
+ - make -j2
+ - printf "FOO=foo\nBAR=bar\nBAZ=baz\nMVENDORID=0\n" >test-env
+ - PROCESSOR_OVERRIDE=rv64 ACCEL=tcg KVM_UNIT_TESTS_ENV=test-env ./run_tests.sh
+      selftest
+      sbi
+      | tee results.txt
+ - grep -q PASS results.txt && ! grep -q FAIL results.txt
+
 build-s390x:
  extends: .outoftree_template
  script: