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[kvm-unit-tests,RFC,02/13] x86/apic: Add MMIO access support for SEV-ES/SNP guest with C-bit unset

Message ID 20240419125759.242870-3-papaluri@amd.com (mailing list archive)
State New, archived
Headers show
Series Introduce SEV-SNP Support | expand

Commit Message

Paluri, PavanKumar April 19, 2024, 12:57 p.m. UTC 
MMIO access to APIC's private GPA with C-bit set that is not backed by
memslots is no longer treated as MMIO access and is treated as an
invalid guest access. So unset the C-bit on APIC page for it to be treated
as a valid MMIO access. This applies to both SEV-ES/SNP guests.

Signed-off-by: Pavan Kumar Paluri <papaluri@amd.com>
---
 lib/x86/apic.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)
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Patch

diff --git a/lib/x86/apic.c b/lib/x86/apic.c
index ed22820784cf..c6305e996a35 100644
--- a/lib/x86/apic.c
+++ b/lib/x86/apic.c
@@ -5,6 +5,8 @@ 
 #include "smp.h"
 #include "asm/barrier.h"
 #include "asm/io.h"
+#include "amd_sev.h"
+#include "x86/vm.h"
 
 /* xAPIC and I/O APIC are identify mapped, and never relocated. */
 static void *g_apic = (void *)APIC_DEFAULT_PHYS_BASE;
@@ -233,7 +235,17 @@  void set_irq_line(unsigned line, int val)
 
 void enable_apic(void)
 {
+	pteval_t *pte;
+
 	printf("enabling apic\n");
+
+	if (amd_sev_es_enabled()) {
+		pte = get_pte((pgd_t *)read_cr3(),
+			      (void *)APIC_DEFAULT_PHYS_BASE);
+
+		*pte &= ~(get_amd_sev_c_bit_mask());
+	}
+
 	xapic_write(APIC_SPIV, 0x1ff);
 }