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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF00036F40.mail.protection.outlook.com (10.167.248.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7452.22 via Frontend Transport; Fri, 19 Apr 2024 12:58:36 +0000 Received: from ethanolx16dchost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 19 Apr 2024 07:58:35 -0500 From: Pavan Kumar Paluri To: CC: Paolo Bonzini , Sean Christophersen , Michael Roth , Tom Lendacky , Pavan Kumar Paluri , "Kim Phillips" , Vasant Karasulli Subject: [kvm-unit-tests RFC PATCH 02/13] x86/apic: Add MMIO access support for SEV-ES/SNP guest with C-bit unset Date: Fri, 19 Apr 2024 07:57:48 -0500 Message-ID: <20240419125759.242870-3-papaluri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240419125759.242870-1-papaluri@amd.com> References: <20240419125759.242870-1-papaluri@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F40:EE_|SJ1PR12MB6337:EE_ X-MS-Office365-Filtering-Correlation-Id: fd974885-6afb-4407-10fc-08dc60706d17 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Apr 2024 12:58:36.1349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fd974885-6afb-4407-10fc-08dc60706d17 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F40.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6337 MMIO access to APIC's private GPA with C-bit set that is not backed by memslots is no longer treated as MMIO access and is treated as an invalid guest access. So unset the C-bit on APIC page for it to be treated as a valid MMIO access. This applies to both SEV-ES/SNP guests. Signed-off-by: Pavan Kumar Paluri --- lib/x86/apic.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/lib/x86/apic.c b/lib/x86/apic.c index ed22820784cf..c6305e996a35 100644 --- a/lib/x86/apic.c +++ b/lib/x86/apic.c @@ -5,6 +5,8 @@ #include "smp.h" #include "asm/barrier.h" #include "asm/io.h" +#include "amd_sev.h" +#include "x86/vm.h" /* xAPIC and I/O APIC are identify mapped, and never relocated. */ static void *g_apic = (void *)APIC_DEFAULT_PHYS_BASE; @@ -233,7 +235,17 @@ void set_irq_line(unsigned line, int val) void enable_apic(void) { + pteval_t *pte; + printf("enabling apic\n"); + + if (amd_sev_es_enabled()) { + pte = get_pte((pgd_t *)read_cr3(), + (void *)APIC_DEFAULT_PHYS_BASE); + + *pte &= ~(get_amd_sev_c_bit_mask()); + } + xapic_write(APIC_SPIV, 0x1ff); }