From patchwork Wed Apr 24 15:49:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13642076 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44AD9161B58 for ; Wed, 24 Apr 2024 15:37:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713973037; cv=none; b=HhmL50JRQueqLpJO7NDs48kTOC7d+VysOyAZsjDrNFQw5riTqhB0ofBxEwkvKP+Bx2Wj4EJlH3Y+m3sPt12AADZcaWKTHPbWQZZ4oc5hUknzt8kRZwC7jdu4TW+P0aaQKE8D4lPT6RJBcORVOtWIMEUp1DCUVd8cqLT4ZmyRgK8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713973037; c=relaxed/simple; bh=Ai1ng+dk0nsRCgPVGEWWIBd3S8WFTfWmnzOyyxvtVb4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DgM1k1mDhfOhmSMJFBlwK19mVDUjtJVEyMM1a/sVx2J1f0+vsYzrFokFC/qrEMBubalXI3xOHWo/LfwLKkbCrf59U4EM3rwAna7428sKpDT0GjxJOOhWJUmS7KpNOQlmq3aMTbdZY4GVQNb31483PYlYNJvhXIc+6EsMBB3Yc2k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QuhS2mzO; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QuhS2mzO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713973036; x=1745509036; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ai1ng+dk0nsRCgPVGEWWIBd3S8WFTfWmnzOyyxvtVb4=; b=QuhS2mzO4fwwFtnOx/JzxneeSQ7cTxUauXP8kxDkRgCrnBxhGdJA/+RH LvZ6opE2oVj2llpDMHWvAbghl6qAwxkV649klIgTgToA3yyuSM8CKvG7P R+09mRd+shc0K0629qx/SvyKD7wEhX5pWc8RijK5tr9zp4B/Qe3cgkTng kRlR2eD1KW0JRXqh1KE629ppf+bCaUoJLOziiM7NFJjRY4BiVrLMHKhQs d9gqR+V6jt5D4q5wvbaGP690gKayB6++oUuHSv3h9TxGcAWRVkGGoidUW 1h9e6Z3FIQtqn4dQ7Wu/On6ks6Zoo2OtwaUBsjP0uwybAOr6vkWlvgIXy w==; X-CSE-ConnectionGUID: 4ppiQQsTStOUb7CoT7kUpQ== X-CSE-MsgGUID: oKVYM3asSiuJo03f3Npd+g== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="12545799" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="12545799" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 08:37:16 -0700 X-CSE-ConnectionGUID: 3B9YI2RnSnmmzkFwSOZOfw== X-CSE-MsgGUID: /aziVApPQdS9+QR0Ls4iwQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="25363328" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa008.jf.intel.com with ESMTP; 24 Apr 2024 08:37:11 -0700 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Babu Moger , Xiaoyao Li , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH v11 16/21] i386/cpu: Introduce module-id to X86CPU Date: Wed, 24 Apr 2024 23:49:24 +0800 Message-Id: <20240424154929.1487382-17-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240424154929.1487382-1-zhao1.liu@intel.com> References: <20240424154929.1487382-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce module-id to be consistent with the module-id field in CpuInstanceProperties. Following the legacy smp check rules, also add the module_id validity into x86_cpu_pre_plug(). Tested-by: Yongwei Ma Co-developed-by: Zhuocheng Ding Signed-off-by: Zhuocheng Ding Signed-off-by: Zhao Liu Tested-by: Babu Moger --- Changes since v7: * Introduced module_id instead of cluster_id. * Dropped Michael/Babu's ACKed/Tested tags since the code change. * Re-added Yongwei's Tested tag For his re-testing. Changes since v6: * Updated the comment when check cluster-id. Since there's no v8.2, the cluster-id support should at least start from v9.0. Changes since v5: * Updated the comment when check cluster-id. Since current QEMU is v8.2, the cluster-id support should at least start from v8.3. Changes since v3: * Used the imperative in the commit message. (Babu) --- hw/i386/x86.c | 33 +++++++++++++++++++++++++-------- target/i386/cpu.c | 2 ++ target/i386/cpu.h | 1 + 3 files changed, 28 insertions(+), 8 deletions(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index fecff4d833c6..b1106ccb1d70 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -343,6 +343,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, cpu->die_id = 0; } + /* + * module-id was optional in QEMU 9.0 and older, so keep it optional + * if there's only one module per die. + */ + if (cpu->module_id < 0 && ms->smp.modules == 1) { + cpu->module_id = 0; + } + if (cpu->socket_id < 0) { error_setg(errp, "CPU socket-id is not set"); return; @@ -359,6 +367,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, cpu->die_id, ms->smp.dies - 1); return; } + if (cpu->module_id < 0) { + error_setg(errp, "CPU module-id is not set"); + return; + } else if (cpu->module_id > ms->smp.modules - 1) { + error_setg(errp, "Invalid CPU module-id: %u must be in range 0:%u", + cpu->module_id, ms->smp.modules - 1); + return; + } if (cpu->core_id < 0) { error_setg(errp, "CPU core-id is not set"); return; @@ -378,16 +394,9 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, topo_ids.pkg_id = cpu->socket_id; topo_ids.die_id = cpu->die_id; + topo_ids.module_id = cpu->module_id; topo_ids.core_id = cpu->core_id; topo_ids.smt_id = cpu->thread_id; - - /* - * TODO: This is the temporary initialization for topo_ids.module_id to - * avoid "maybe-uninitialized" compilation errors. Will remove when - * X86CPU supports module_id. - */ - topo_ids.module_id = 0; - cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids); } @@ -432,6 +441,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, } cpu->die_id = topo_ids.die_id; + if (cpu->module_id != -1 && cpu->module_id != topo_ids.module_id) { + error_setg(errp, "property module-id: %u doesn't match set apic-id:" + " 0x%x (module-id: %u)", cpu->module_id, cpu->apic_id, + topo_ids.module_id); + return; + } + cpu->module_id = topo_ids.module_id; + if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { error_setg(errp, "property core-id: %u doesn't match set apic-id:" " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a637a8ad8f51..76085ec007fa 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8102,12 +8102,14 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), + DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), #else DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), + DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), #endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b0ecf90460ab..042eec417d0f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2059,6 +2059,7 @@ struct ArchCPU { int32_t node_id; /* NUMA node this CPU belongs to */ int32_t socket_id; int32_t die_id; + int32_t module_id; int32_t core_id; int32_t thread_id;