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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF0000014A.mail.protection.outlook.com (10.167.244.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7544.18 via Frontend Transport; Mon, 29 Apr 2024 06:07:26 +0000 Received: from BLR-5CG113396H.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Apr 2024 01:07:17 -0500 From: Ravi Bangoria To: , , , , , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH 2/3] x86/bus_lock: Add support for AMD Date: Mon, 29 Apr 2024 11:36:42 +0530 Message-ID: <20240429060643.211-3-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240429060643.211-1-ravi.bangoria@amd.com> References: <20240429060643.211-1-ravi.bangoria@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|CH3PR12MB8581:EE_ X-MS-Office365-Filtering-Correlation-Id: 5a9530dc-3624-4a4f-64c3-08dc6812a503 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|7416005|82310400014|376005|36860700004; X-Microsoft-Antispam-Message-Info: pb+AqvPlYVq3kAZ7bubZkZxHU8KhW/68EdBnQYfQGXfmhgNTvTzACYkJ+9ftCtUlBCPgCUP2UXrYghtj8bWyawQSvz6rSNwbDIFbsh4kTnEP34rY7tYR/1+VLJ4CxrDheq27reX0hxE99tK2N64Sr2gpr4uE18vbHtZ7LTJKIMiyou7AHdHGzRwNdvye0fW+oHN8vi/Dykb4qu2TaaVS6XUqEb/24b+/WUUp/PYO4bgcqYblpG4Dvkow8k35P7PHbZ0oOyUrLGFELqe8INAHwzagJ6vMcYwCfmFr1/NwxVE+hwPdy4zjMNB7qraYGemTfq4HFwRZ+KSocqCsut58D48uJ8snEhTwDEbgRAWIiB7YBKOdpchQrLIyenNQSxmifKxEKpJVgUuefCZLWaLtyidB1xSw8DC1HFpMDlqBi6gLDVoGN64zR4lro3XCqfvr9ADOLwx6zecycJXjuC0euoSy3sjZx9RBv1xARQMr5xYx768jvDVb7qKr09Up9nT31GPLoUxA8zGGcTlDjwzNmMirKtHRGvAS9xO249+Nz06zphGESXXJ9sRNHOdFIelix7LU3kvq+qMQZlIA2bt6FNGFoQmLh/DU5zmn40kzAZbJr2lUzEy4d33Qc79Tvfxk2pPSdIONLAiaN0ppD5LSMbyD0Lib+SsO3hyrBvgd8Y3CvOofo8FlqEoCQVnUUBY6MM+qusAeBTprxilwmhQx/dkC15m8A2nTMs7WbcYv6qeN200JUQq05OTPQqvWb8dlBembKO/aoQckptG4QJUZfV30PV+Fu0fV2hFrdbvqrVtPFcmhMvvvIZrloYx5DmuDd7EN3XRCLXlc4iCd0Q26I4i69qblg5uMZkyj2xOBEdR2h+Vgn9fO32bmMXeMkiF4F6lvX1WgpdOt50DFT4zjpZwgm4MFddi9vXJk5UeyfP+9Rz2jJnfegCmg6EShuCVjttcs4+eUry4VVQfdyYGP0qTbLk0c9zWWXkoYm6ZfHTrheHkgTeUyYl4IuUjdcJ5TYbv+YicveoeMIr7R6TEKpsA74w/ch4rdPxwmTszrylR6IdvwD9fxnKa/KK8j443Ydh35LTqXxW9Okom//gmBYEto3+rAy4r0p23dCIhrEPSkA6wwUcJhqiO9noIndXUZi2WFj0Bhqagkg6CLsG3kQzdtQI7jPDg9/aOEdUnpLzPr/AaXc43KphtaBpG1ithObFY2EEgPv5tseIcaYok503izFUE7Hcoq9zx+8/+H7eKYPktB+URIIxhjdcq+UbXzdXDPkb6BObmyNF1g9NmX9euk9jpDL78LqDCgJ5UU44zTJv1btkPIcAqf9kQxbESd X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(1800799015)(7416005)(82310400014)(376005)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2024 06:07:26.1774 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a9530dc-3624-4a4f-64c3-08dc6812a503 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8581 Upcoming AMD uarch will support Bus Lock Detect (called Bus Lock Trap in AMD docs). Add support for the same in Linux. Bus Lock Detect is enumerated with cpuid CPUID Fn0000_0007_ECX_x0 bit [24 / BUSLOCKTRAP]. It can be enabled through MSR_IA32_DEBUGCTLMSR. When enabled, hardware clears DR6[11] and raises a #DB exception on occurrence of Bus Lock if CPL > 0. More detail about the feature can be found in AMD APM[1]. [1]: AMD64 Architecture Programmer's Manual Pub. 40332, Rev. 4.07 - June 2023, Vol 2, 13.1.3.6 Bus Lock Trap https://bugzilla.kernel.org/attachment.cgi?id=304653 Signed-off-by: Ravi Bangoria --- arch/x86/kernel/cpu/amd.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 39f316d50ae4..013d16479a24 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1058,6 +1058,8 @@ static void init_amd(struct cpuinfo_x86 *c) /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); + + bus_lock_init(); } #ifdef CONFIG_X86_32