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b=OuP1SyS9Bwv5pJ3GzF3bJJGh686S9rKQhkroLNVM4jRZBu3mlz7wed4YnYaPS4vl1v EUC68u3AcbvNz2ntFdLAt0Yo6i7T3mrb3QImLky6jzwArVjYB/z4D4yJGcZA39El4YcJ OOqi+UGAsOhgpzXUHXY/7pzklgkCgotnOwACCpUPvQITZDgt6doSGJdnBnmM79fXZzlm EzJiINBsk2+Idy0I0Wuig2A0RU4C6Xxz6LvduTEfkua48BDpEktAjcsa7ofBkox+yWEn EzHvBpxxO1iqfpTDaVb50TFKMQafQdE4qgJIne9Uc5PcQ0SUZbrJ8YrePqoOhKdIAHjI h5Lw== X-Forwarded-Encrypted: i=1; AJvYcCV8pKUEHabBJiHHUYcBtov1HCLnfzpXjQW2OmqaL9QdJs4NSmynvLCQ2Sd42/vqk8wvcbZ0oK5jG3dTA24S8AdYd/71 X-Gm-Message-State: AOJu0YyiNv1v/uy952CXHz+Ao9NEZK3GrkGcWBQjZhaFmGjKxIpvdi0q uLL+liR+hW5st24zcob1lCuLVKZxCNZumO5o1Wb8ltgfObRxxFVDuOj/AEFTi01JviF1563IcTh IaQc+sw== X-Google-Smtp-Source: AGHT+IEoDoKL6bIcsKXu5g80INJRprO1/lLAhr+CEcEGoJrqGc2N33Bj0ShzzTtaYaOJs/MTq2tsW/TfUFFh X-Received: from mizhang-super.c.googlers.com ([35.247.89.60]) (user=mizhang job=sendgmr) by 2002:a05:6a00:39a1:b0:6ec:ceb4:d9e2 with SMTP id fi33-20020a056a0039a100b006ecceb4d9e2mr239424pfb.0.1714973449476; Sun, 05 May 2024 22:30:49 -0700 (PDT) Reply-To: Mingwei Zhang Date: Mon, 6 May 2024 05:29:37 +0000 In-Reply-To: <20240506053020.3911940-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240506053020.3911940-1-mizhang@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240506053020.3911940-13-mizhang@google.com> Subject: [PATCH v2 12/54] perf: x86: Add x86 function to switch PMI handler From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , Peter Zijlstra , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org From: Xiong Zhang Add x86 specific function to switch PMI handler since passthrough PMU and host PMU use different interrupt vectors. x86_perf_guest_enter() switch PMU vector from NMI to KVM_GUEST_PMI_VECTOR, and guest LVTPC_MASK value should be reflected onto HW to indicate whether guest has cleared LVTPC_MASK or not, so guest lvt_pc is passed as parameter. x86_perf_guest_exit() switch PMU vector from KVM_GUEST_PMI_VECTOR to NMI. Signed-off-by: Xiong Zhang Signed-off-by: Dapeng Mi --- arch/x86/events/core.c | 17 +++++++++++++++++ arch/x86/include/asm/perf_event.h | 3 +++ 2 files changed, 20 insertions(+) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 09050641ce5d..8167f2230d3a 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -701,6 +701,23 @@ struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data) } EXPORT_SYMBOL_GPL(perf_guest_get_msrs); +void x86_perf_guest_enter(u32 guest_lvtpc) +{ + lockdep_assert_irqs_disabled(); + + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_GUEST_PMI_VECTOR | + (guest_lvtpc & APIC_LVT_MASKED)); +} +EXPORT_SYMBOL_GPL(x86_perf_guest_enter); + +void x86_perf_guest_exit(void) +{ + lockdep_assert_irqs_disabled(); + + apic_write(APIC_LVTPC, APIC_DM_NMI); +} +EXPORT_SYMBOL_GPL(x86_perf_guest_exit); + /* * There may be PMI landing after enabled=0. The PMI hitting could be before or * after disable_all. diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 3736b8a46c04..807ea9c98567 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -577,6 +577,9 @@ static inline void perf_events_lapic_init(void) { } static inline void perf_check_microcode(void) { } #endif +void x86_perf_guest_enter(u32 guest_lvtpc); +void x86_perf_guest_exit(void); + #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data); extern void x86_perf_get_lbr(struct x86_pmu_lbr *lbr);